Patents by Inventor Bor Lee
Bor Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961762Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: June 30, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Publication number: 20240108954Abstract: Lacrosse shafts are provided that include graphene. The graphene increases the durability of the lacrosse shafts. Also provided is equipment for other contact sports that include graphene to increase durability.Type: ApplicationFiled: December 8, 2023Publication date: April 4, 2024Inventors: Hamilton Sean Michael WHITNEY, Gregory Lee KENNEALLY, Chia-Jen HSU, Bor Z. JANG, Aruna ZHAMU
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Patent number: 11929422Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: GrantFiled: July 29, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11881530Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: GrantFiled: January 24, 2022Date of Patent: January 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Publication number: 20230411279Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.Type: ApplicationFiled: June 21, 2022Publication date: December 21, 2023Inventors: Liang-Hsuan PENG, Chih-Hung LU, Chih-Lin WANG, Song-Bor LEE
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Publication number: 20230411455Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: ApplicationFiled: August 9, 2023Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Publication number: 20230387302Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi PENG, Song-Bor LEE
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Patent number: 11824089Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: GrantFiled: January 24, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Publication number: 20230307522Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.Type: ApplicationFiled: April 3, 2023Publication date: September 28, 2023Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
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Publication number: 20230256161Abstract: Methods for treating a disease condition in a subject are provided. The subject methods are characterizing by enhancing at least one symptom of the disease condition in a manner effective to cause the subject to mount a compensatory response effective to treat the disease condition. Also provided are compositions, kits and systems for practicing the subject methods.Type: ApplicationFiled: January 5, 2021Publication date: August 17, 2023Inventors: Anthony Joonkyoo Yun, Patrick Yuarn-Bor Lee
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Patent number: 11695055Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.Type: GrantFiled: March 3, 2020Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11621343Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.Type: GrantFiled: July 19, 2021Date of Patent: April 4, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Wen-Yuan Chen, Wen-Hsing Hsieh, Yi-Ju Hsu, Jon-Hsu Ho, Song-Bor Lee, Bor-Zen Tien
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Publication number: 20220384613Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second SID regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Lid.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Publication number: 20220336276Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Patent number: 11450567Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: October 30, 2020Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Patent number: 11389534Abstract: Methods are provided for treating a subject for at least one condition that includes inflammation, a blood clotting condition and autonomic nervous system dysfunction such as adrenergia, e.g., simultaneously. Also provided are kits for use in practicing the subject methods.Type: GrantFiled: August 27, 2018Date of Patent: July 19, 2022Assignee: Palo Alto InvestorsInventors: Anthony Joonkyoo Yun, Patrick Yuarn-Bor Lee
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Publication number: 20220149178Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: CHENG-YI PENG, Song-Bor LEE
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Publication number: 20220149155Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi PENG, Song-Bor LEE
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Patent number: 11233149Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: GrantFiled: March 3, 2020Date of Patent: January 25, 2022Inventors: Cheng-Yi Peng, Song-Bor Lee
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Patent number: 11233119Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: GrantFiled: March 2, 2020Date of Patent: January 25, 2022Inventors: Cheng-Yi Peng, Song-Bor Lee