Abstract: The present invention provides a method of forming a dielectric layer on a semiconductor wafer. The semiconductor wafer comprises a bottom dielectric layer and a plurality of metal lines each having a rectangular cross section positioned on the bottom dielectric layer. The method is performed in a high-density plasma chemical vapor deposition apparatus. A first deposition process at a first etching/deposition (E/D) ratio is performed to form a first dielectric layer with a predetermined thickness on the semiconductor wafer. The first dielectric layer covers the surface of the metal lines and forms a triangular ridge above each metal line. The upper side of each of the ridges has two slanted side-walls. Then, a second deposition process at a second E/D ratio is performed to form a second dielectric layer with a predetermined thickness on the semiconductor wafer with the second deposition process etching rate being near zero.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an electron-beam process, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: A method of deposition with 4-PASS which is performed by a WJ-1000 or WJ-999 machine. Before each deposition is performed, it is necessary to turn the wafer an angle of 90.degree. in the same direction. When deposition is this manner is performed four times on the same wafer, the uniformity in the four corners of the layer deposited on the 8-inch wafer can be improved. Over-polishing or recesses can be reduced and the kink effect can be prevented. 4-PASS deposition performed on the WJ-1000 or WJ-999 machine can make the uniformity within the wafer better and the yield of production can be increased.

Abstract: A method of removing residual contaminants in grooves of an alignment mark of a semiconductor wafer after a chemical-mechanical polishing is disclosed. The method includes scrubbing the semiconductor wafer using conventional scrubbing technique. Next, the semiconductor wafer is etched back to remove a damaged layer, which is formed during the chemical-mechanical polishing, over the semiconductor wafer. Finally, the semiconductor wafer is cleaned, for example, by NH.sub.4 OH/H.sub.2 O.sub.2 /DI, agitated by a megasonic source, thereby substantially removing the residual contaminants from the alignment mark.

Abstract: A method of preventing overpolishing in a chemical-mechanical polishing operation includes using a spin-on polymer material instead of spin-on glass as the local planarization material. The spin-on polymer layer is further used as a polishing stop layer so as to prevent damage to components due to overpolishing, because the polishing rate of the spin-on polymer layer in a chemical-mechanical polishing operation is, in general, lower than the polishing rate of the silicon dioxide layer formed using plasma enhanced chemical vapor deposition.

Abstract: A method of fabricating a trench isolation structure in a semiconductor devices. First, a mask layer is formed on a substrate and patterned. Then, a trench is formed in the substrate using the mask layer as a mask. An insulating layer is formed under the mask layer to fill the trench. The insulating layer is polished to expose a portion of the mask layer and an insulating plug is left in the trench. A RTP is performed to avoid mobile ions diffuse into the substrate. There are several operating conditions for the RTP. For example the operating temperature is ranged from about 600.degree. C. to about 1300.degree. C. The duration for performing the RTP is ranged from about 5 seconds to about 5 minutes. The operating gas can be selected from one of a group of N.sub.2, O.sub.2, or N.sub.2 O. Besides, before the RTP a cleaning step is performed using SC-1 or hydrogen fluoride (HF) solution as cleaning solution.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: A semiconductor fabrication method is provided for the fabrication of a shallow-trench isolation (STI) structure in integrated circuit. Conventionally, the insulating plug of the STI structure would be undesirably formed with microscratches in its top surface resulting from chemical-mechanical polishing (CMP) process, thus causing an undesired bridging effect thereacross when conductive layers are subsequently formed. This method can help solve this problem by forming a mending dielectric layer over the insulating plug of the STI structure to mend these microscratches. Since the mending dielectric layer is in a flowable state when it is being coated over the wafer, it can fill up all the microscratches in the top surface of the insulating plug, thereby mending the microscratches to prevent the bridging effect across the insulating plug that would other-wise occur in the case of the prior art.

Abstract: A method for forming a barrier layer inside a contact in a semiconductor wafer is disclosed herein. The forgoing semiconductor wafer includes a dielectric layer on a silicon contained layer. A portion of the silicon contained layer is exposed by the contact. The method mentioned above includes the following steps.First, form a conductive layer on the topography of the semiconductor wafer by a method other than CVD to increase the ohmic contact to the exposed silicon contained layer. Thus a first portion of the conductive layer is formed on the dielectric layer, and a second portion of the conductive layer is formed on the exposed silicon contained layer. Next, remove the first portion of the conductive layer to expose the dielectric layer. Finally, use a chemical vapor deposition (CVD) method to form the barrier layer on the dielectric layer and the first portion of the conductive layer to prevent said silicon contained layer from exposure.

Abstract: A method of forming a conductive plug is disclosed. A device with a conductive region is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. The insulating layer is etched to form a contact window which exposes the conductive region of the device. A diffusion barrier layer is formed on the exposed conductive region and the periphery of the contact window. A hydrogen plasma treatment is performed in a reaction chamber; and a conductive material is filled in the contact window, to form the conductive plug.

Abstract: A method for planarizing interlayer dielectric is disclosed. The present invention includes firstly forming a barrier layer over a semiconductor substrate. Next, a buffer layer is formed on the barrier layer by a spin-on-glass technique. A dielectric layer is formed on the buffer layer, wherein etch rate of the dielectric layer is larger than etch rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the dielectric layer. Finally, the dielectric layer is etched back using the buffer layer as buffer, thereby planarizing the dielectric layer.

Abstract: A method for treating via sidewalls comprising the steps of providing a substrate having a number of metallic wires already formed; depositing a liner oxide layer; depositing an organic spin-on-glass layer; and depositing a second oxide layer. The second oxide layer is planarized by a chemical-mechanical polishing method. Photolithographic and etching methods, employing oxygen plasma treatment as well as a wet etching removal method are used to form vias above the metallic layers. A hydrogen plasma treatment is performed for the via sidewalls to prevent the occurrence of out-gassing and to obtain superior electrical properties. A titanium/titanium nitride film is deposited, and aluminium or tungsten is deposited into the vias and to form aluminium or tungsten plugs, thus completing the manufacturing process according to this invention. A semiconductor device formned by this method is also described.

Abstract: A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature.