Abstract: A method for training a time-domain equalizer having at least one coefficient that includes estimating a channel, initializing the at least one coefficient of the time-domain equalizer, updating the at least one coefficient of the time-domain equalizer with the estimated channel, retaining the updated estimated channel, fixing the updated value of the at least one coefficient of the time-domain equalizer for at least a one-symbol duration, calculating a modulated symbol based on an output of the time-domain equalizer, calculating a second value for the estimated channel based on the modulated symbol, setting the estimated channel to the second value, and repeating the step of updating the time-domain equalizer through the step of setting the estimated channel to the second value until a predetermined condition has been met.

Abstract: An all-digital phase-locked loop is disclosed which comprises: (a) a digital control oscillator for receiving a local signal and generating an output signal to be locked in with an input signal, (b) a K-counter for providing first control signals to the digital control oscillator; (c) a phase frequency detector for receiving and comparing the output signal received from the digital control oscillator and the input signal, and providing second control signals to the K-counter according to a detected difference between the input and output signals. In the all-digital phase-locked loop, the digital control oscillator comprises a delay line, an address generator and a multiplexer. The delay line comprises a plurality of identical flip-flops each having a phase delay of about 2&pgr;/L, L being the number of stages of the delay line, and a trigger clock, which is connected to the shift registers, so as to generate a plurality of phase-different clocks.

Abstract: A Fast Fourier Transform device of a discrete multitone modulation system can be implemented by very large scale integrated (VLSI) architecture. The I-FFT/F-FFT functions are modified to avoid complex-valued operations. A time recursive parallel lattice structure is used to reduce the complexity in hardware requirement for the I-FFT/F-FFT.

Abstract: An all-digital phase-locked loop (ADPLL) device includes a primary ADPLL circuit and a controller which allow an in-phase output signal to be generated even when the incoming reference signal is lost. The primary ADPLL loop includes a phase detector, a digital loop filter, a first digital control oscillator (DCO) for generating a loop signal which is phase-locked to a received reference signal, and a frequency divider. The controller generates control signals to be used by a secondary DCO or the first DCO to generate a synchronized system output signal. The controller includes an accumulator which accumulates the number of phase-hopping events performed by the first DCO for a certain time period, a first-in-first-out (FIFO) buffer which stores a number of consecutive phase-hopping samples from the accumulator, and a calculator for determining an average of the consecutive values stored in the FIFO buffer.

Abstract: An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time .PHI.; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: ##EQU1## The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.

Abstract: A system for canceling network pointer adjustment jitters (PAJs). The system is equipped with an elastic buffer to receive, according to a write clock signal, and for temporarily storing a plurality of data bits in the buffer and a pointer interpreter for determining a pointer adjustment event (PAE) and a polarity of bit-stuffing from the data bits. The jitter-cancellation system includes a leaking rate control signal generator for generating a leaking rate control based on the PAE and a polarity signal based on the polarity of bit stuffing. The jitter-cancellation system further includes a phase hopping control device for applying the write clock signal, the leaking rate control signal and the polarity signal for performing a phase-hopping read clock adjustment to generate a read clock signal for controlling a bit-leaking from the elastic buffer such that the bit-leaking is controlled to release in a fraction of a phase step, i. e., a phase of (2.pi./n) for each bit of the data.

Abstract: A system and method are disclosed for reducing waiting time jitter in a pulse-stuffing multiplexer of a communications network. The data of a lower rate signal, that is plesiochronous with a higher rate signal into which the lower rate signal is to be multiplexed, is written into an elastic buffer in accordance with a write signal that is derived from the data of the lower rate signal. The data is read out of the elastic buffer in accordance with a read signal which is locally generated. A comparison circuit forms the phase difference between the write and read signals. A justification circuit generates a justification signal with pulses corresponding to the instances where the phase difference exceeds a dynamically randomly varying threshold. The pulses of the justification signal, in turn, regulate the reading out of the data of the lower rate signal from the elastic buffer.