Abstract: The structure and manufacturing method of a non-volatile semiconductor memory device are provided. The method for manufacturing a cell stack includes steps of: (a) providing a substrate; (b) forming on the substrate an oxide layer, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially; (c) etching back to form a first recess pattern; (d) filling with a second dielectric layer; (e) depositing a third dielectric layer; (f) depositing a fourth dielectric layer; (g) etching to form a second recess pattern; (h) depositing a barrier layer on the second recess pattern; and (i) filling with a third conductive layer. The proposed structure of a cell stack includes a substrate, an oxide layer, a first stack, a second dielectric layer, a second stack, a third dielectric layer, and a fourth dielectric layer.

Abstract: A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprise a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate and is etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded in low dielectric material, the coupling capacitance produced therein will be greatly reduced.

Abstract: A conductive contact structure to electrically connect to a source/drain region in a semiconductor substrate and a process of making the same. An inlay opening including a pad opening and a bottom opening is formed in the dielectric layer on the semiconductor substrate. The pad opening is larger than and located upon the bottom opening that exposes the source/drain region. The bottom opening and pad opening are sequentially filled with a polysilicon layer and a tungsten layer to form a bottom plug and a metal pad layer, respectively.

Abstract: The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer.

Abstract: A memory device with composite contact plug and method for manufacturing the same. The composite contact plug comprises a first insulating layer deposited on a semiconductor substrate. A contact hole is formed to penetrate through the first insulation layer. A barrier layer is deposited in the contact hole and fills a portion of the contact hole. A contact plug is formed on the barrier layer and fills the contact hole. The first insulating layer is etched back until the surface of the first insulating layer is below the contact plug. A diffusion barrier layer is then deposited on the first insulating layer and the contact plug. The diffusion barrier layer is planarized until the contact plug is exposed to form a composite contact plug. The memory device is constructed on the composite contact plug.

Abstract: A conductive contact structure to electrically connect to a source/drain region in a semiconductor substrate and a process of making the same are described. An inlay opening including a pad opening and a bottom opening is formed in the dielectric layer on the semiconductor substrate. The pad opening is larger than and located upon the bottom opening that exposing the source/drain region. The bottom opening and pad opening are sequentially filled with a polysilicon layer and a tungsten layer to form a bottom plug and a metal pad layer, respectively.

Abstract: The structure and manufacturing method of a non-volatile semiconductor memory device are provided. The method for manufacturing a cell stack includes steps of: (a) providing a substrate; (b) forming on the substrate an oxide layer, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially; (c) etching back to form a first recess pattern; (d) filling with a second dielectric layer; (e) depositing a third dielectric layer; (f) depositing a fourth dielectric layer; (g) etching to form a second recess pattern; (h) depositing a barrier layer on the second recess pattern; and (i) filling with a third conductive layer. The proposed structure of a cell stack includes a substrate, an oxide layer, a first stack, a second dielectric layer, a second stack, a third dielectric layer, and a fourth dielectric layer.

Abstract: A stacked spacer structure and process adapted for a stacked layer on a semiconductor substrate is described. The stacked spacer structure is formed on the sidewalls of the stacked layer which comprising a conductive layer and a cap layer thereon. A dielectric layer made of a material with low dielectric constant lower than that of silicon nitride is formed on the semiconductor substrate. A first silicon nitride layer is then formed over the substrate. The first silicon nitride layer and dielectric layer are etched sequentially to form an inner spacer on the sidewalls of the stacked layer. A second silicon nitride layer is formed over the substrate, and etched to form an outer spacer on the sidewalls of the inner spacer. By forming the stacked spacer structure of the present invention embedded low dielectric material, the coupling capacitance produced therein will be greatly reduced.

Abstract: The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer.

Abstract: A memory device with composite contact plug and method for manufacturing the same. The composite contact plug comprises a first insulating layer deposited on a semiconductor substrate. A contact hole is formed to penetrate through the first insulation layer. A barrier layer is deposited in the contact hole and fills a portion of the contact hole. A contact plug is formed on the barrier layer and fills the contact hole. The first insulating layer is etched back until the surface of the first insulating layer is below the contact plug. A diffusion barrier layer is then deposited on the first insulating layer and the contact plug. The diffusion barrier layer is planarized until the contact plug is exposed to form a composite contact plug. The memory device is constructed on the composite contact plug.

Abstract: The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer.

Abstract: The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer.

Abstract: A capacitor formed on a conductive plug of a semiconductor substrate has a composite storage node, wherein a Ru conductive layer covers the conductive plug and a conductive oxide layer with a perovskite structure covers the Ru conductive layer. A capacitor dielectric layer covers the composite storage node. An electrode layer covers the capacitor dielectric layer.

Abstract: A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

Abstract: A fabrication method for a self-aligned contact opening involves using polysilicon to protect a cap layer above a conductive line or even a corner of a spacer on a sidewall of the conductive line. A silicon oxide layer is then etched using a conventional silicon oxide etching recipe to form a self-aligned contact opening. This conventional silicon oxide etching recipe not only has a higher etching selectivity for silicon oxide to silicon nitride, but also yields a higher etching selectivity ratio for silicon oxide to polysilicon.

Abstract: A method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer.