Patents by Inventor Bor-Shyang LIAO

Bor-Shyang LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9685316
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: June 20, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 9318338
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (Pt)-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin
  • Patent number: 8993390
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 31, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Publication number: 20150050799
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (PO-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Bor-Shyang Liao, Tsung-Hsun Tsai, Kuo-Chih Lai, Pin-Hong Chen, Chia-Chang Hsu, Shu-Min Huang, Min-Chung Cheng, Chun-Ling Lin
  • Patent number: 8877635
    Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: November 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
  • Publication number: 20140248762
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Publication number: 20140242802
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 8815738
    Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Chang Hsu, Bor-Shyang Liao, Kuo-Chih Lai, Nien-Ting Ho, Chi-Mao Hsu, Shu-Min Huang, Min-Chung Cheng
  • Patent number: 8766319
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Patent number: 8765588
    Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
  • Publication number: 20140017888
    Abstract: A salicide process is described. A substrate having thereon an insulating layer and a silicon-based region is provided. A nickel-containing metal layer is formed on the substrate. A first anneal process is performed to form a nickel-rich silicide layer on the silicon-based region. The remaining nickel-containing metal layer is stripped. A thermal recovery process is performed at a temperature of 150-250° C. for a period longer than 5 minutes. A second anneal process is performed to change the phase of the nickel-rich silicide layer and form a low-resistivity mononickel silicide layer.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chang Hsu, Bor-Shyang Liao, Kuo-Chih Lai, Nien-Ting Ho, Chi-Mao Hsu, Shu-Min Huang, Min-Chung Cheng
  • Patent number: 8598033
    Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.
    Type: Grant
    Filed: October 7, 2012
    Date of Patent: December 3, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Bor-Shyang Liao, Chun-Ling Lin, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Publication number: 20130288456
    Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
    Type: Application
    Filed: April 26, 2012
    Publication date: October 31, 2013
    Inventors: Kuo-Chih Lai, Chia Chang Hsu, Nien-Ting Ho, Bor-Shyang Liao, Shu Min Huang, Min-Chung Cheng, Yu-Ru Yang
  • Publication number: 20130273736
    Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
  • Patent number: 8541303
    Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 24, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
  • Patent number: 8450624
    Abstract: The invention provides a supporting substrate and method for fabricating the same. The supporting substrate includes: a substrate; a first surface metal layer formed on the substrate, wherein the first surface metal layer has a first opening; a second surface metal layer formed on the substrate and disposed oppositely to the first surface metal layer, wherein the substrate has a through hole, and the through hole is formed along the first opening to expose the second surface metal layer; a protective layer formed on the first surface metal layer and the second surface metal layer, wherein the protective layer has a second opening which exposes the through hole; and a conductive bump formed in the through hole, the first opening and the second opening, wherein the conductive bump is electrically connected to the second surface metal layer.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: May 28, 2013
    Assignee: Nan Ya PCB Corp.
    Inventors: Meng-Han Lee, Shao-Yang Lu, Bor-Shyang Liao
  • Publication number: 20130078800
    Abstract: A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Kuo-Chih Lai, Nien-Ting Ho, Shu Min Huang, Bor-Shyang Liao, Chia Chang Hsu
  • Publication number: 20130078792
    Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Inventors: Pong-Wey Huang, Chan-Lon Yang, Chang-Hung Kung, Wei-Hsin Liu, Ya-Hsueh Hsieh, Bor-Shyang Liao, Teng-Chun Hsuan, Chun-Yao Yang
  • Publication number: 20110253440
    Abstract: The invention provides a supporting substrate and method for fabricating the same. The supporting substrate includes: a substrate; a first surface metal layer formed on the substrate, wherein the first surface metal layer has a first opening; a second surface metal layer formed on the substrate and disposed oppositely to the first surface metal layer, wherein the substrate has a through hole, and the through hole is formed along the first opening to expose the second surface metal layer; a protective layer formed on the first surface metal layer and the second surface metal layer, wherein the protective layer has a second opening which exposes the through hole; and a conductive bump formed in the through hole, the first opening and the second opening, wherein the conductive bump is electrically connected to the second surface metal layer.
    Type: Application
    Filed: August 10, 2010
    Publication date: October 20, 2011
    Applicant: NAN YA PCB CORP.
    Inventors: Meng-Han LEE, Shao-Yang LU, Bor-Shyang LIAO