Abstract: An apparatus and method for transferring hidden signals in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected, and then an output of a second data is generated when a second predetermined input stream is detected, wherein the second predetermined input stream is different from the first one and also conforms to the invalid state transition loop.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Then, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the internal register for rotating data of the internal register to a first position in accordance with written unaligned address. A store combine register is coupled to the rotator for temporarily storing data of the rotator. A mask selector is coupled to the rotator and the store combine register for selectively masking their data in accordance with the written unaligned address and storing the data masked to the memory.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with plural N-bit registers, a shifter to combine a first and a second output contents of the register unit to form a 2N-bit word and shift the word by w bits, thereby outputting first N bits of the word shifted, a controller to set the register unit in accordance with the multiple shift instruction decoded, thereby reading contents of corresponding registers for shifting w bits by the shifter and then writing an output of the shifter to the register unit.

Abstract: A device and method of applying a parity to encrypt data for protection is disclosed. A parity generator generates a parity bit in accordance with a data to be outputted. A first parity location generator generates an inserting position N for the parity bit in accordance with a predetermined algorithm. A parity-inserting unit inserts the parity bit in a position between (N?1)th and Nth-bit of the data in accordance with the inserting position N, thereby generating an encrypted data.

Abstract: A device of applying protection bit codes to encrypt a program for protection is disclosed. The program has a plurality of instructions P (positive integer). The device includes a protection-bit-code generator, a first protection-bit-code location generator and a protection-bit-code insertion unit. The protection-bit-code generator generates a plurality of protection bit codes in accordance with the plurality of instructions of the program, wherein each instruction has a plurality of bits I (positive integer). The first protection-bit-code location generator generates a plurality of insertion positions N (positive integer) for each protection bit code in accordance with processor status when executing the program.

Abstract: A system and method of applying a parity bit to protect transmitting and receiving data is disclosed. The system includes a transmitting-end device and a receiving-end device. The transmitting-end device includes a parity generator, a first parity location generator and a parity inserting unit which, when transmitting data, inserts a parity bit in the data to thus generate an encrypted data. The receiving-end device includes a second parity location generator and a parity removal unit that receives the encrypted data and removes Nth bit of the encrypted data in accordance with an inserting position N generated by the second parity location generator.

Abstract: A device and method of applying check bit to encrypt instruction for protection is disclosed. The device has a check-bit generator, a first check-bit location generator and a check-bit insertion unit. The check-bit generator generates a check bit in accordance with an instruction with a plurality of bits to be outputted. The first check-bit location generator generates an insertion position N (positive integer) for the check bit in accordance with the instruction and a predetermined algorithm. The check-bit insertion unit inserts the check bit in a position between (N-1)th- and Nth-bit of the instruction in accordance with the insertion position N generated by the first check bit location generator, thereby generating an encrypted instruction.

Abstract: A method and an architecture capable of adaptively accessing data and instructions are provided, in which a plurality of data transfer levels are predefined and a current data transfer level is used for accessing data and instructions of a memory. Each data transfer level corresponds to a length of a continuous data transfer via an interface between the memory and a cache device. Thus, the invention can dynamically adjust the current data transfer level based on burst lengths actually occurred as a processor kernel accesses data/instructions.

Abstract: A device and method for scrambling data by means of address lines is disclosed, which includes a seed generator, a first parameter generator, a data scrambler and a de-scrambler. The seed generator is connected to an address bus for generating a seed in accordance with a specific address on the address bus. The first parameter generator is connected to the seed generator for generating a first parameter based on the seed. The data scrambler is connected to a data bus for scrambling data based on the first parameter when a CPU core is to write the data to the specific address. The de-scrambler is connected to the data bus for de-scrambling the data based on the first parameter when the core is to read the data from the specific address.

Abstract: A processor device and method for data protection by means of data block scrambling is disclosed, which has a processor core, a cache and a block scrambling/de-scrambling device. The processor core executes instructions of the processor and access data in a memory. The cache is connected to the processor core in order to provide it with a memory space for quickly accessing data. The block scrambling/de-scrambling device is coupled between the cache and the memory in order to scramble data block outputted by the cache based on a seed generated by a seed generator or to de-scramble data block inputted by the memory based on the seed.

Abstract: A device and method for data protection by scrambling address lines is disclosed, which includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The area check unit compares an address of address bus with addresses of first data area or redundancy area stored in the redundancy area-setting unit and accordingly generates a comparison result. The address-mapping unit converts the address of address bus into an address of redundancy area. The multiplexer outputs the address of redundancy area when the comparison result and a switch control signal are logic true; otherwise the address of address bus is output.

Abstract: A method and an architecture capable of programming and controlling access of data and instructions are provided. There are provided a plurality of data transfer levels, in which a current data transfer level is used for accessing data and instructions from an external memory. Each data transfer level corresponds to a length of a continuous data transfer via an interface between the memory and a high-speed access device. The current data transfer level is dynamically adjusted based on data format accessed by a processor kernel or a result of instruction decoding performed by the processor kernel.

Abstract: A processor and method capable of executing conditional instructions is disclosed, which can execute an instruction set including M-bit instructions and N-bit instructions. The instruction set has condition execution instructions and M-bit parallel condition execution instructions. Each parallel condition execution instruction has a first and a second N-bit instruction. An instruction fetching device fetches at least one instruction to be performed. An instruction decoder decodes the instruction fetched by the instruction fetching device. An instruction executing device executes the instruction outputted by the instruction decoder, wherein a flag is set according to a result of executing a condition execution instruction. A mode switching device switches the instruction decoder to decode one of the first and the second N-bit instructions according to the state of the flag, so as to be subsequently performed by the instruction executing device, when a parallel condition execution instruction is fetched.

Abstract: A processor and method using parity check to switch instruction modes is disclosed, which can execute in N-bit and 2N-bit modes. The processor includes an instruction input device, an instruction fetch device and a mode switch logic. The instruction input device includes a memory having a width of 2N bits for storing a plurality of 2N-bit words. The instruction fetch device fetches a 2N-bit word. The mode switch logic determines whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction, and accordingly switches the processor to corresponding N-bit or 2N-bit mode. When the 2N-bit word fetched is even parity, the 2N-bit word is determined as two (N-P)-bit instructions if two N-bit words included in the 2N-bit word are on the first parity state, or determined as a 2(N-P)-bit instruction if the two N-bit words are on the second parity state.

Abstract: There is disclosed an architecture capable of accessing data and instructions of an external memory device using store and forward, which has a processor kernel, a cache module, a prefetch module, a switch, and a store and forward controller. The switch is provided for switching a connection from the processor kernel to the cache module or the prefetch module. The store and forward controller detects access between the prefetch module and the memory device, so as to command the switch to switch the connection from the processor kernel to the prefetch module when the prefetch module transfers data by burst transfer, such that data and instructions transferred from the memory device to the prefetch module are also transferred to the processor kernel.

Abstract: A method and an architecture capable of adaptively accessing data and instructions are provided, in which a plurality of data transfer levels are predefined and a current data transfer level is used for accessing data and instructions of a memory. Each data transfer level corresponds to a length of a continuous data transfer via an interface between the memory and a cache device. Thus, the invention can dynamically adjust the current data transfer level based on burst lengths actually occurred as a processor kernel accesses data/instructions.

Abstract: A method and an architecture capable of programming and controlling access of data and instructions are provided. There are provided a plurality of data transfer levels, in which a current data transfer level is used for accessing data and instructions from an external memory. Each data transfer level corresponds to a length of a continuous data transfer via an interface between the memory and a high-speed access device. The current data transfer level is dynamically adjusted based on data format accessed by a processor kernel or a result of instruction decoding performed by the processor kernel.