Patents by Inventor Bor-Tyng Lin

Bor-Tyng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9853630
    Abstract: A flip-flop includes a master latch configured to receive a data signal and a scan input signal. The master latch provides one of the data signal or the scan input signal to a slave latch based on a scan enable signal. The flip-flop includes circuitry configured to generate clock signals based on one or both of an input clock signal and the scan enable signal. A first clock signal is provided to the master latch and a second clock signal is provided to the slave latch. The first clock signal does not include edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a first logic level. The first clock signal includes edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jerry Chang-Jui Kao, Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh, Bor-Tyng Lin
  • Publication number: 20170141766
    Abstract: A flip-flop includes a master latch configured to receive a data signal and a scan input signal. The master latch provides one of the data signal or the scan input signal to a slave latch based on a scan enable signal. The flip-flop includes circuitry configured to generate clock signals based on one or both of an input clock signal and the scan enable signal. A first clock signal is provided to the master latch and a second clock signal is provided to the slave latch. The first clock signal does not include edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a first logic level. The first clock signal includes edge transitions that occur at same times as edge transitions of the second clock signal when the scan enable signal has a second logic level.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Inventors: Jerry Chang-Jui Kao, Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh, Bor-Tyng Lin