Abstract: Apparatus and method for processing wide dynamic range (WDR) image are disclosed. The WDR image processing apparatus could be integrated within an image sensor or an image backend apparatus. Whether the m-th bit of the sensing image signal is equal to 1 is determined. If the m-th bit is equal to 1, then the values corresponding to the m-th to the (m?r)-th bits are added by first offset to output a WDR image signal. If the m-th bit is not equal to 1, then whether the (m?1)-th bit is equal to 1 is determined. If the (m?1)-th bit is equal to 1, then the values corresponding to the (m?1)-th to the (m?s)-th bits are added by a second offset to output the WDR image signal. The same processing is applied up to the (m?t)-th bit, m, n, r, s and t are positive integers, and m is greater than n.

Abstract: Apparatus and method for processing wide dynamic range (WDR) image are disclosed. The WDR image processing apparatus could be integrated within an image sensor or an image backend apparatus. Whether the m-th bit of the sensing image signal is equal to 1 is determined. If the m-th bit is equal to 1, then the values corresponding to the m-th to the (m?r)-th bits are added by first offset to output a WDR image signal. If the m-th bit is not equal to 1, then whether the (m?1)-th bit is equal to 1 is determined. If the (m?1)-th bit is equal to 1, then the values corresponding to the (m?1)-th to the (m?s)-th bits are added by a second offset to output the WDR image signal. The same processing is applied up to the (m?t)-th bit, m, n, r, s and t are positive integers, and m is greater than n.

Abstract: A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.

Abstract: A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.

Abstract: A full duplex DES cipher processor (DCP) supports to execute sixteen rounds of data encryption standard (DES) operation in four encryption modes and four decryption modes, namely: Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode, and Output Feedback (OFB) mode for both encryption and decryption. A DCP is composed of an I/O unit, an IV/key storage unit, a control unit, and an algorithm unit. The algorithm unit is used to encrypt/decrypt the incoming text message. The algorithm unit having a crypto engine allows encryption and decryption performed alternately, by sharing the same crypto engine. Since for crypto applications in communication services like T1, E1, V.35, the algorithm unit operation time is much shorter than the data I/O time; in other word, the algorithm unit is in the idle state mostly.