Patents by Inventor Bor-Yeu Tsaur

Bor-Yeu Tsaur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010045927
    Abstract: An active matrix color sequential liquid crystal display has an active matrix circuit, a counterelectrode panel and an interposed layer of liquid crystal. The active matrix circuit has an array of transistor circuits formed in a first plane. Each transistor circuit is connected to a pixel electrode in an array of pixel electrodes having a small area. The counterelectrode panel extends in a second plane that is parallel to the first plane, such that the counterelectrode panel receives an applied voltage. The liquid crystal layer is interposed in a cavity between the two planes. In a preferred embodiment, an oxide layer extends over the pixel electrode array. The oxide can have a first thickness in a peripheral region around the array of the pixel electrodes and a thinner second thickness in a pixel electrode region extending over the array of pixel electrodes.
    Type: Application
    Filed: October 31, 1997
    Publication date: November 29, 2001
    Inventors: MATTHEW ZAVRACKY, WEN-FOO CHERN, HIAP L. ONG, JOHN C. C. FAN, BOR-YEU TSAUR, ALAN RICHARD
  • Patent number: 5091333
    Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.
    Type: Grant
    Filed: September 7, 1988
    Date of Patent: February 25, 1992
    Assignee: Massachusetts Institute of Technology
    Inventors: John C. C. Fan, Bor-Yeu Tsaur, Ronald P. Gale, Frances M. Davis
  • Patent number: 5066610
    Abstract: Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in present in cap fracture and enhancing crystal quality but is also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.
    Type: Grant
    Filed: September 22, 1989
    Date of Patent: November 19, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Chenson K. Chen, Bor-Yeu Tsaur
  • Patent number: 4889583
    Abstract: Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in preventing cap fracture and enhancing crystal quality but it also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: December 26, 1989
    Assignee: Massachusetts Institute of Technology
    Inventors: Chenson K. Chen, Bor-Yeu Tsaur
  • Patent number: 4864378
    Abstract: A method and resultant device is described for fabricating iridium silicide Schottky IR detectors in which a thin intermediate film of platinum is formed between the conventional iridium outer layer over a p-type silicon substrate with or without an n-type guard ring. After thermal treatment, an iridium platinum silicide region is formed in the silicon substrate. The unreated iridium/platinum outside the device region is removed using a dry-etching process.
    Type: Grant
    Filed: October 21, 1987
    Date of Patent: September 5, 1989
    Assignee: Massachusetts Institute of Technology
    Inventor: Bor-Yeu Tsaur
  • Patent number: 4853076
    Abstract: An improved method and apparatus for optimizing the electrical properties while crystallizing material is disclosed. In this invention, a material which is to be crystallized is formed on a substrate and subjected to a heat treatment to intentionally induce thermal stress while crystallizing the material. The heat treatment melts the material being crystallized and when the material solidifies, a built-in stress is retained which, in the case of n-doped Si on fused silica results in a tensile stress which produces an electron mobility in the film of 870 cm.sup.2 /volt-sec as compared to similarly fashioned unstressed n-doped Si on SiO.sub.2 coated Si which has an electron mobility of 500 cm.sup.2 /volt-sec.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: August 1, 1989
    Assignee: Massachusetts Institute of Technology
    Inventors: Bor-Yeu Tsaur, John C. C. Fan, Michael W. Geis
  • Patent number: 4774205
    Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO.sub.2 and Si.sub.3 N.sub.4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si.sub.3 N.sub.4 /SiO.sub.2 layers and final metallization is performed to complete the MOSFET fabrication.
    Type: Grant
    Filed: June 13, 1986
    Date of Patent: September 27, 1988
    Assignee: Massachusetts Institute of Technology
    Inventors: Hong K. Choi, Bor-Yeu Tsaur, George W. Turner
  • Patent number: 4700461
    Abstract: A self-aligned integrated JFET device is described wherein an oxide extension region and a doped polysilicon gate is used as part of a self-aligned mask to form drain and source regions. Asymmetric JFETs for power circuit applications can be made in accordance with the invention. Additionally, complementary enhancement mode JFETs can be made in accordance with the invention, for low power consumption and excellent radiation-hardened characteristics.
    Type: Grant
    Filed: September 29, 1986
    Date of Patent: October 20, 1987
    Assignee: Massachusetts Institute of Technology
    Inventors: Hong-Kyun Choi, Bor-Yeu Tsaur
  • Patent number: 4670088
    Abstract: An improved method and apparatus for crystallizing amorphous or polycrystalline material is disclosed. In this invention, a material which is to be crystallized is formed on a substrate and single crystalline seed material is disposed in contact and/or adjacent to or with at least a portion of the material which is to be crystallized. A layer of material which serves as a "wetting agent" is then formed over the material to be crystallized. The structure thus formed is subjected to a heat treatment which melts the material being crystallized and when the material solidifies its crystalline structure is substantially epitaxial based on the seed material. The "wetting agent" layer serves to prevent deleterious balling up of the material during crystallization.
    Type: Grant
    Filed: February 11, 1986
    Date of Patent: June 2, 1987
    Assignee: Massachusetts Institute of Technology
    Inventors: Bor-Yeu Tsaur, John C. C. Fan, Michael W. Geis
  • Patent number: 4632712
    Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.
    Type: Grant
    Filed: December 4, 1984
    Date of Patent: December 30, 1986
    Assignee: Massachusetts Institute of Technology
    Inventors: John C. C. Fan, Bor-Yeu Tsaur, Ronald P. Gale, Frances M. Davis
  • Patent number: 4371421
    Abstract: An improved method and apparatus for crystallizing amorphous or polycrystalline material is disclosed. In this invention, a material which is to be crystallized is formed on a substrate and single crystalline seed material is disposed adjacent and in contact with at least a portion of the material which is to be crystallized. A layer of material which serves as a "wetting agent" is then formed over the material to be crystallized. The structure thus formed is subjected to a heat treatment which melts the material being crystallized and when the material solidifies its crystalline structure is substantially epitaxial based on the seed material. The "wetting agent" layer serves to prevent deleterious balling up of the material during crystallization.
    Type: Grant
    Filed: April 16, 1981
    Date of Patent: February 1, 1983
    Assignee: Massachusetts Institute of Technology
    Inventors: John C. C. Fan, Michael W. Geis, Bor-Yeu Tsaur