Abstract: An integrated circuit (10) provides analog and digital circuitry on a common substrate (12). A first digital circuit (14) operates in combination with an analog circuit (18) to perform a useful function. A second duplicate digital circuit (26) is disposed adjacent to the first digital circuit and operates out-of-phase with respect to the first digital circuit. The second duplicate digital circuit introduces voltage spikes equal and opposite to the voltage spikes introduced into the substrate by the first digital circuit. The equal and opposite voltage spikes tend to cancel and thereby minimize cross-talk between the digital and analog circuits. A guard ring (16,28) surrounds each of the first and second digital circuits and the analog circuit to reduce voltage spikes into the substrates. By minimizing cross-talk, the analog circuit operates without interference from the digital circuits.

Abstract: An SOI wafer (10) is separated into a bipolar junction transistor area (18) and an MOS transistor area (19). A bipolar junction transistor having a collector region (25), and emitter region (44), an inactive base region (33), and an active base region (43) is formed on a thin film of semiconductor material (13) in the bipolar junction transistor area (18). A link between the inactive base region (33) and the active base region (43) is formed from a polysilicon spacer (42) along an edge or sidewall of emitter openings (39 or 40). Simultaneously with the formation of the bipolar junction transistor, MOS transistors are formed in the MOS transistor area (19). Electrically conductive contacts (56) in the bipolar junction transistor area (18) and the MOS transistor area (19) are formed from a silicide. Both complementary bipolar junction transistors and MOS transistors may be formed.

Abstract: A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.

Abstract: A bipolar memory array arranged in a row and column matrix is responsive to a plurality of word line driver transistors for selecting one row of memory cells thereof. The current flowing through each memory cell is provided by a pair or lateral PNP transistor current source loads. The collectors of the word line driver transistors are commonly connected for distributing the source of collector current flowing therethrough between the bases of all of the laterla PNP transistor current sources of the entire memory array which maintains a constant current flow through each of the memory cells during the select and deselect cycles thereby maintaining a constant memory cell array power dissipation which allows for expanded capacity of the memory array and a performance improvement.

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased.

Abstract: An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.

Abstract: An improved means and method for forming an optical sensor within an integrated circuit structure is described. An epi-coated semiconductor wafer is masked and a cavity etched through the epi-layer to the underlying substrate. A dielectric sidewall is formed on the cavity sidewall and a substantially intrinsic semiconductor region, preferably grown by selective epitaxy, to refill the cavity. The upper surface of the intrinsic region is then heavily doped and contacted by a low resistance polysilicon layer which is substantially transparent to incoming light. The method forms a high sensitivity PIN photo-sensor having a thick space-charge region for efficient capture of the hole-electron pairs produced by the incoming light. The fabrication techniques are compatible with the processing requirements for other integrated circuit devices formed on the same chip and to which the PIN device is coupled without wire bonds, tabs, bumps or the like.

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: An active load for a CML or ECL logic gate for substantially increasing the speed of the gate comprises a transistor having its base coupled to its collector by a first resistor, and its collector-emitter path coupled in series with a second resistor. This load provides an inductive impedance when the small signal emitter resistance is less than the sum of the resistance of the base and the first resistor, causing a peaking effect resulting in high switching speed.

Abstract: A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.