Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

Abstract: According to various embodiments, an electronic device comprises: at least one processor; and memory operatively connected to the at least one processor, wherein the memory may store instructions which, when executed by the at least one processor, cause the electronic device to: obtain, from a kernel, at least one address for a first memory area accessible through the kernel; store the at least one address in a second memory area accessible through a hypervisor; based on obtaining an address stored in a kernel stack from the kernel, identify whether the obtained address is defective, on the basis of the at least one stored address; and restore the defective address using at least one address stored in the second memory area in response to identifying the defect in the address.

Abstract: A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.

Abstract: Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

Abstract: In various embodiments, an electronic device may include: a processor including a plurality of cores, and a memory connected to the processor. The memory may store instructions which, when executed, cause the processor to, based on an abort of an execution of an instruction in a first core among the plurality of cores, determine whether a second core capable of executing the instruction exists in the plurality of cores, and to transfer the execution of the instruction to the second core, based at least on determining that the second core exists among the plurality of cores.