Patents by Inventor Boram IM

Boram IM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11514954
    Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: November 29, 2022
    Inventors: Boram Im, Hongsoo Kim, Jongkook Park, Hose Choi, Hyunju Sung
  • Publication number: 20220130430
    Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.
    Type: Application
    Filed: June 1, 2021
    Publication date: April 28, 2022
    Inventors: Boram Im, Hongsoo Kim, Jongkook Park, Hose Choi, Hyunju Sung
  • Patent number: 10388604
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Publication number: 20180233450
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 16, 2018
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Patent number: 9978684
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changseop Yoon, Hyung Jong Lee, Boram Im
  • Publication number: 20160293546
    Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.
    Type: Application
    Filed: March 28, 2016
    Publication date: October 6, 2016
    Inventors: Changseop YOON, Hyung Jong LEE, Boram IM