Abstract: The present invention increases efficiency of a binary translation process by correlating selected foreign code to previously translated binary host code. This approach eliminates repetitive translation of foreign code when the foreign code is executed on a host computer system. During the translation process, a database of translated foreign code is populated and thereafter a software layer checks for correspondence between the foreign code and binary code stored in the database. If the database contains corresponding code, that code is transferred to system memory for execution and there is no need to retranslate the foreign code. Minimizing the time spent translating the foreign code results in improved execution speed on the host computer system. The software layer creates an index into the database by hashing the foreign code or by using the storage location of the foreign code. By way of example, the sector of a disk drive where the foreign code is stored determines the index into the database.

Abstract: The present invention relates to a microprocessor based computer system having binary translation support to achieve high performance without compatibility problems. The computer system includes a support software layer that enables the execution of foreign application and operating system software without degradation during execution. The support software layer includes an emulated foreign supervisor flag and means for porting foreign software including the operating system to the host platform. The host platform includes host and foreign virtual space spaces and two page tables supported in hardware to minimize the time required for translation between virtual to physical addresses. A flag in a page table entry marks pages in the virtual memories having data that is accessible only to the host platform's supervisor. When the computer system processor is not operating in a foreign supervisor mode, an attempt to access the virtual space generates an exception trap.

Abstract: The present invention relates to a computer system adapted to efficiently execute binary translated code. In accordance with the present invention, foreign code is stored in a foreign virtual memory space, translated to acquire binary translated code, which is stored in a host virtual memory space and then executed. The host computer system isolates each virtual memory configuration into separate processes referred to as a virtual machine while enabling multiple virtual machines to exist simultaneously. Execution may switch from one virtual machine to another merely by switching to a new page table, where each page table describes the memory configuration of a virtual machine. Common system level resources are shared by the virtual machines under the control of a virtual memory manager.

Abstract: A method, implemented in a compiler, of balancing the workload between blocks in a control flow to reduce the overall execution time of control block includes steps for identifying “hard” blocks the consume excess resources, selecting hard block to unload, and unloading critical operations from a hard block to a control flow predecessor.

Abstract: A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.

Abstract: The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array preload unit provides continuous preliminary loading of data arrays located in a memory subsystem into a prefetch buffer. Array loading is performed asynchronously with respect to execution of the main program.

Abstract: For certain classes of software pipelined loops, prologue and epilogue portions of adjacent inner loops in a nested loop can be overlapped. In this way, outer loop code, as well as inner loop code, can be software pipelined. Architectural support for software pipelined nested loops is provided by a set of loop parameter and status registers and by an implementation of loop state dependent, multiway control transfers. For loop body code compatible with two simple constraints, the present invention does not require additional code elements for disabling garbage operations during prologue and epilogue loop periods of adjacent inner loops. Nested loop control allows overlap between the epilogue period of a prior inner loop and the prologue period of a next inner loop. As a result, nested loop code can be more efficiently scheduled by a compiler for execution on a processor such as VLIW processor which provides architectural support for software pipelined nested loops, thereby providing improved loop performance.

Abstract: An array prefetch system improves processor performance by automatically tuning a statically compiled and compacted loop program at run-time to accommodate variations in latency of memory read operations. Using the array prefetch system, the processor, while awaiting completion of a data access, continues to generate requests for subsequent iterations rather than fully halting execution until a read access is finished.

Abstract: For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible with two simple constraints, code elements are not required for disabling garbage operations during prologue and epilogue loop periods. As a result, resources associated with implementation of the powerful architectural feature of predicated execution need not be squandered to service loop control. In particular, neither increased instruction width nor an increased number of instructions in the loop body is necessary to provide loop control in accordance with the present invention. Fewer service functions are required in the body of a loop. As a result, loop body code can be more efficiently scheduled by a compiler and, in some cases, fewer instructions will be required, resulting in improved loop performance.

Abstract: A central processor for scientific-technica, economic-statistical computations, for solving the problems of modelling and control with the architecture of an extended instruction work comprises instruction data buffer memories 1 and 3, respectively, a control device 2, a data commutator 4, an arithmeticologic device 5, record-calling, indexing, associative memory, mathematical-to-physical address conversion, interface, subprogram device (6-11), as well as a control character device 13 and an operand readiness device 14, and provides high efficiency both on vector and scalar computations.