Abstract: In one embodiment, interconnect element (IE) circuitry electrically interconnects electronic components (e.g., a transceiver and a filter or a filter and an antenna). The IE circuitry has an inductive signal path and a grounded, inductive return path, where at least one actively controlled impedance-compensation element, electrically interconnecting the signal and ground paths, is controllable to selectively provide different impedance levels, such that overall impedance of the IE circuitry is controllable to achieve low pass-band insertion loss and high stop-band attenuation between the electronic components without requiring expensive RF connectors to connect the IE circuitry to the electronic components and an RF filter to provide stop-band attenuation. In a T-filter configuration, the IE circuitry has only one impedance-compensation element; in a Pi-filter configuration, the IE circuitry has two impedance-compensation elements.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: In one embodiment, interconnect element (IE) circuitry electrically interconnects electronic components (e.g., a transceiver and a filter or a filter and an antenna). The IE circuitry has an inductive signal path and a grounded, inductive return path, where at least one actively controlled impedance-compensation element, electrically interconnecting the signal and ground paths, is controllable to selectively provide different impedance levels, such that overall impedance of the IE circuitry is controllable to achieve low pass-band insertion loss and high stop-band attenuation between the electronic components without requiring expensive RF connectors to connect the IE circuitry to the electronic components and an RF filter to provide stop-band attenuation. In a T-filter configuration, the IE circuitry has only one impedance-compensation element; in a Pi-filter configuration, the IE circuitry has two impedance-compensation elements.

Abstract: An embodiment of the disclosed MIMO transceiver uses a single master clock to generate (i) the sampling-clock signals for the analog-to-digital and digital-to-analog converters and (ii) the multiple electrical local-oscillator signals that are used in various channels of the transceiver's analog down- and up-converters to translate signals between the corresponding intermediate-frequency and RF bands. The MIMO transceiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signals and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. In embodiments designed for operating in the mmW band, the MIMO transceiver may also employ a frequency multiplier configured to multiply the master-clock frequency to generate an additional local-oscillator signal for translating signals between the mmW and RF bands.

Abstract: An embodiment of the disclosed MIMO transceiver uses a single master clock to generate (i) the sampling-clock signals for the analog-to-digital and digital-to-analog converters and (ii) the multiple electrical local-oscillator signals that are used in various channels of the transceiver's analog down- and up-converters to translate signals between the corresponding intermediate-frequency and RF bands. The MIMO transceiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signals and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. In embodiments designed for operating in the mmW band, the MIMO transceiver may also employ a frequency multiplier configured to multiply the master-clock frequency to generate an additional local-oscillator signal for translating signals between the mmW and RF bands.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: An embodiment of the disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies.

Abstract: In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one Nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency. A digital-to-analog converter (DAC) digitizes an analog input signal based on the filtered clock signal. Attenuating noise in the Nyquist zones reduces jitter of the filtered clock signal, and passing at least one harmonic frequency of the clock signal other than the fundamental frequency limits the degradation of the slew rate of the clock signal. As a result, the filtered clock signal increases the signal-to-noise ratio of the output of the DAC.

Abstract: An optoelectronic receiver having a variable transfer function to compensate for operational condition change. The receiver comprises a linear circuit having a tunable filter. A control circuit provides a signal to the tunable filter. The control circuit is connected to one or more sensors which sense one or more operational conditions. The control circuit signal is a function of the one or more sensed operational conditions. The control signal is input to the tunable filter which adjusts the linear circuit's transfer function based on the control signal. Further disclosed are an integrated circuit and optical communication system having the inventive optoelectronic receiver. A method for adjusting an optoelectronic signal in a receiver is also disclosed.

Abstract: An optoelectronic receiver having a variable transfer function to compensate for operational condition change. The receiver comprises a linear circuit having a tunable filter. A control circuit provides a signal to the tunable filter. The control circuit is connected to one or more sensors which sense one or more operational conditions. The control circuit signal is a function of the one or more sensed operational conditions. The control signal is input to the tunable filter which adjusts the linear circuit's transfer function based on the control signal. Further disclosed are an integrated circuit and optical communication system having the inventive optoelectronic receiver. A method for adjusting an optoelectronic signal in a receiver is also disclosed.

Abstract: A transceiver is disclosed for use in a wireless handset. The transceiver includes a switch for connecting an antenna, one at a time, to a receiver or to a transmitter. In a reception sub-frame, a limiting circuit switches the switch to an attenuated mode when an output signal of the receiver, such as a logarithmic RSSI signal, exceeds a predetermined value. The limiting circuit includes a comparator for comparing the logarithmic RSSI signal with the predetermined value. In addition, the limiting circuit also includes a transistor which shunts to ground a first control input of the switch when the RSSI signal exceeds the predetermined value. The limiting circuit further includes a shunt circuit to maintain the attenuated mode during a transmission sub-frame to reduce the level of a signal from the transmitter.