Abstract: The present disclosure provides systems and techniques in which an ambient may be controlled on the basis of a current status of a micro-processed substrate so as to maintain the status within predefined limits. In illustrative embodiments, the substrate may be stored in an ambient, for which temperature and/or contents of one or more gaseous species may be controlled so as to reduce the change of status. Consequently, in particular, queue times may be significantly prolonged, thereby imparting superior flexibility to scheduling the overall process flow in a complex manufacturing environment.

Abstract: The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.

Abstract: A method comprises depositing a first portion of a first material layer on a semiconductor structure. A first run of a post-treatment process is performed for modifying at least the first portion of the first material layer. After the first run of the post-treatment process, a second portion of the first material layer is deposited. The second portion is formed of substantially the same material as the first portion. After the deposition of the second portion of the first material layer, a second run of the post-treatment process is performed for modifying at least the second portion of the first material layer.

Abstract: When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.

Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device on a semiconductor substrate includes selectively implanting dopant ions to form implants in the semiconductor substrate. Trenches are formed in the semiconductor substrate and the trenches are filled with an isolation material. An upper surface of the isolation material is established substantially coplanar with the semiconductor substrate. In the method, the implants and the isolation material are then simultaneously annealed.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.

Abstract: High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy.

Abstract: High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy.

Abstract: Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned.