Abstract: A circuit includes a clock generator for providing a clock signal to a synchronously operated digital circuit and a control signal generator for providing a control signal to the synchronously operated digital circuit. The control signal generator is interconnected to the clock generator to suppress the clock signal for a defined duration as a control signal is provided. The defined duration allows the control signal to settle to allow said synchronously operated digital circuit to unambiguously sample said control signal. The control signal generator may place the synchronous digital circuit in a lower power consumption state.

Abstract: A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices. The alignment logic may operate to adjust one or more communicated signals, so that signals that may have different propagation times arrive at one or more devices at a desired time. The system and method may be used when initializing a communication system and before communicating data. The system and method operate to adjust one or more signals, such as a data strobe signal in a memory system for example, so that the one or more signals arrive at one or more devices spaced apart in time within a defined tolerance at a desired time. The alignment logic is used to compensate for signal propagation delays which can be associated with a signal propagation path.

Abstract: A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference voltage circuit, coupled to external fixed reference voltage, includes control logic and an array of switchable resistor elements (pull-up and pull-down resistors) that may each be selectively switched in or out of the circuit to change the reference voltage being supplied to an on-chip receiver.

Abstract: A circuit includes a clock generator for providing a clock signal to a synchronously operated digital circuit and a control signal generator for providing a control signal to the synchronously operated digital circuit. The control signal generator is interconnected to the clock generator to suppress the clock signal for a defined duration as a control signal is provided. The defined duration allows the control signal to settle to allow said synchronously operated digital circuit to unambiguously sample said control signal. The control signal generator may place the synchronous digital circuit in a lower power consumption state.

Abstract: A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices. The alignment logic may operate to adjust one or more communicated signals, so that signals that may have different propagation times arrive at one or more devices at a desired time. The system and method may be used when initializing a communication system and before communicating data. The system and method operate to adjust one or more signals, such as a data strobe signal in a memory system for example, so that the one or more signals arrive at one or more devices spaced apart in time within a defined tolerance at a desired time. The alignment logic is used to compensate for signal propagation delays which can be associated with a signal propagation path.

Abstract: A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference voltage circuit, coupled to external fixed reference voltage, includes control logic and an array of switchable resistor elements (pull-up and pull-down resistors) that may each be selectively switched in or out of the circuit to change the reference voltage being supplied to an on-chip receiver.

Abstract: A sorting-type toy comprising a series of angularly spaced compartments, each separated by a divider having an aperture therethrough. A plurality of colored or otherwise identifiable balls are located in the compartments and are sorted by the user through the apertures until all balls of one type or alignment are located in each of the compartments.

Abstract: A multilevel rotary maze comprising a series of stacked maze elements which are rotatable relative to one another. Each of the elements has a series of apertures, at least one of the apertures passing therethrough, and at least a portion of the apertures define a serpentine path throughout the maze which can be attained upon selective sequential rotation of the maze elements to align predetermined apertures thereof. A ball is located in the maze to pass through the apertures as they are aligned.

Abstract: A removable insert for a mold for impressing indicia on each molded product formed in the mold. The insert includes a plug body, a bore through the plug body, and a plug situated in the bore and having a mold engaging surface for impressing an article formed in the mold. The plug is rotatable and include an indicator which may be directed toward a series of indicia spaced about the periphery of the bore.