Patents by Inventor Boris Feigin
Boris Feigin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12373339Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.Type: GrantFiled: January 29, 2024Date of Patent: July 29, 2025Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Ying Gao, Boris Feigin
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Patent number: 12282686Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.Type: GrantFiled: March 27, 2023Date of Patent: April 22, 2025Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Boris Feigin, Ying Gao, John Colgrove
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Patent number: 12271359Abstract: A storage system is provided. The storage system include a primary storage node that includes a primary processing device. The primary storage node is communicatively coupled to a secondary storage node. The secondary storage node includes a secondary processing device and a set of non-volatile memory modules. The primary processing device is to identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node and transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device.Type: GrantFiled: March 1, 2023Date of Patent: April 8, 2025Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Ying Gao, Boris Feigin, Robert Lee
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Patent number: 12236117Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.Type: GrantFiled: September 1, 2023Date of Patent: February 25, 2025Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
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Patent number: 12229437Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.Type: GrantFiled: June 3, 2022Date of Patent: February 18, 2025Assignee: PURE STORAGE, INC.Inventors: Ying Gao, Boris Feigin, Hari Kannan
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Patent number: 12093545Abstract: A storage system has a first memory, a second memory that include solid-state storage memory, and a processing device. The processing device is to select a mode for each portion of data to be written. Selection of the mode is based at least on size of the portion of data. Selection of the mode is from among modes that include a first mode of writing the portion of data in mirrored RAID form to the first memory for later transfer from the first memory to the second memory, a second mode of writing the portion of data in parity-based RAID form to the first memory for later transfer from the first memory to the second memory, and a third mode of writing the portion of data to the second memory, bypassing the first memory. The processing device is to handle portions of data to be written according to such selection.Type: GrantFiled: January 6, 2022Date of Patent: September 17, 2024Assignee: PURE STORAGE, INC.Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano, Svitlana Tumanova
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Patent number: 12067282Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes selecting one of a plurality of write paths for incoming data, and writing the incoming data via the selected write path. A first write path includes writing to NVRAM, writing from NVRAM to SLC flash memory and writing from SLC flash memory to QLC flash memory. A second write path includes writing to NVRAM and writing from NVRAM to QLC flash memory, bypassing SLC flash memory. A third write path includes writing to SLC flash memory, bypassing NVRAM, and writing from SLC flash memory to QLC flash memory.Type: GrantFiled: June 2, 2022Date of Patent: August 20, 2024Assignee: PURE STORAGE, INC.Inventors: Ying Gao, Boris Feigin, Hari Kannan
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Patent number: 12056386Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.Type: GrantFiled: March 17, 2023Date of Patent: August 6, 2024Assignee: PURE STORAGE, INC.Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano
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Patent number: 12046292Abstract: A method of using boot-time metadata in a storage system is provided. The method includes writing a fragmentation stride to a solid-state storage device of the storage system, the fragmentation stride defining a granularity on which fragmentation of erase blocks of the solid-state storage device occurs. The method includes allocating portions of erase blocks for at least one process in the storage system, in accordance with the fragmentation stride and writing boot up metadata at offsets that are based on the fragmentation stride, in the solid-state storage device.Type: GrantFiled: May 12, 2021Date of Patent: July 23, 2024Assignee: PURE STORAGE, INC.Inventors: Radek Aster, Andrew R. Bernat, Boris Feigin, Ronald Karr, Robert Lee
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Patent number: 11947814Abstract: A storage system determines a change in storage system geometry that affects at least one previously formed resiliency group of storage system resources. The storage system forms at least one resiliency group of storage system resources in accordance with rules that emphasize stability of formation of resiliency groups. The storage system accesses data stripes across storage system resources of resiliency groups.Type: GrantFiled: September 27, 2021Date of Patent: April 2, 2024Assignee: PURE STORAGE, INC.Inventors: Ian Juch, Haijie Xiao, Hao Liu, Boris Feigin
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Patent number: 11886334Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.Type: GrantFiled: June 2, 2022Date of Patent: January 30, 2024Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Ying Gao, Boris Feigin
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Patent number: 11853266Abstract: A system for cloud-based file services, comprising: a plurality of single-tenant file system nodes configured to provide file system access to an object store via a plurality of multitenant storage nodes; the plurality of multitenant storage nodes sharing access to the object store; and one or more management nodes configured to provision resources for the plurality of single-tenant file system nodes and the plurality of multitenant storage nodes, including modifying resources within the system.Type: GrantFiled: July 18, 2022Date of Patent: December 26, 2023Assignee: PURE STORAGE, INC.Inventors: Robert Lee, Igor Ostrovsky, Mark Emberson, Boris Feigin, Ronald Karr
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Patent number: 11847324Abstract: A storage system establishes a staging region, for temporary writing of arriving data, and a stable region, for transfer of data from the staging region, in storage memory. The storage system establishes resiliency groups, each with a characteristic level of redundancy that is settable on an individual basis. The storage system performs data accesses of data stripes in accordance with the staging region, the stable region, a first resiliency group and a second resiliency group.Type: GrantFiled: October 27, 2021Date of Patent: December 19, 2023Assignee: PURE STORAGE, INC.Inventors: Robert Lee, Boris Feigin, Ying Gao, Ronald Karr
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Patent number: 11789626Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.Type: GrantFiled: September 28, 2022Date of Patent: October 17, 2023Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
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Patent number: 11782625Abstract: A method of operating a storage system, and related storage system, are provided. The storage system establishes resiliency groups, each having a defined level of redundancy of resources of the storage system. The resiliency groups include at least one compute resources resiliency group and at least one storage resources resiliency group. The storage system supports capability of configurations that have multiples of each of the resiliency groups. Blades of the storage system perform distributed data and metadata storage across modular storage devices, in accordance with the resiliency groups.Type: GrantFiled: July 19, 2021Date of Patent: October 10, 2023Assignee: PURE STORAGE, INC.Inventors: Robert Lee, Boris Feigin, Ying Gao, Ronald Karr
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Patent number: 11714572Abstract: A redundant array of independent drives (RAID) stripe is formed across a set of storage controllers of a plurality of storage controllers, wherein the RAID stripe comprises two or more of a plurality of modular storage devices of at least one of the set of storage controllers. The RAID stripe is written across the set of storage controllers.Type: GrantFiled: June 8, 2020Date of Patent: August 1, 2023Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Robert Lee, Yuhong Mao, Ronald Karr, Boris Feigin
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Patent number: 11681448Abstract: Fabric modules in a storage system offer differing device IDs from a deterministic sequence to a storage device being added to the storage system. The storage device that is being added accepts a device ID that is higher in the deterministic sequence. The fabric module that offered the device ID same as was accepted by the storage device determines to proceed with initializing the storage device.Type: GrantFiled: October 12, 2021Date of Patent: June 20, 2023Assignee: PURE STORAGE, INC.Inventors: Ian Juch, Hao Liu, Boris Feigin, Haijie Xiao, Gordon James Coleman
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Patent number: 11614880Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.Type: GrantFiled: December 31, 2020Date of Patent: March 28, 2023Assignee: PURE STORAGE, INC.Inventors: Ying Gao, Boris Feigin, Hari Kannan, Igor Ostrovsky, Jeffrey Tofano
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Patent number: 11614893Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.Type: GrantFiled: January 27, 2021Date of Patent: March 28, 2023Assignee: PURE STORAGE, INC.Inventors: Hari Kannan, Boris Feigin, Ying Gao, John Colgrove
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Publication number: 20230024480Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.Type: ApplicationFiled: September 28, 2022Publication date: January 26, 2023Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin