Patents by Inventor Boris Gommershtadt

Boris Gommershtadt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176293
    Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: November 16, 2021
    Assignee: Synopsys, Inc.
    Inventors: Dmitry Korchemny, Alexander Rabinovitch, Boris Gommershtadt, Daniel Geist, Srivatsan Raghavan
  • Patent number: 11138356
    Abstract: A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 5, 2021
    Assignee: Synopsys, inc.
    Inventors: Alex Potapov, Boris Gommershtadt, Yan Zucker
  • Patent number: 11106663
    Abstract: A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 31, 2021
    Assignee: Synopsys, Inc.
    Inventors: Ilya Kudryavtsev, Daniel Geist, Boris Gommershtadt
  • Publication number: 20210232742
    Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.
    Type: Application
    Filed: January 26, 2021
    Publication date: July 29, 2021
    Inventors: Dmitry Korchemny, Nathaniel Azuelos, Boris Gommershtadt, Alexander Shot
  • Patent number: 10962595
    Abstract: Coverage event counters for hardware verification emulations are implemented as linear feedback shift register-based counters generating encoded counter values indicative of a detected number of coverage events. To decode those counter values, a counter algorithm utilized to generate the encoded counter value may continue to be iterated after counting is complete until reaching a defined pattern, while counting the number of iterations (K) necessary to reach the defined pattern. The resulting counter value having the defined pattern is correlated with a mapping table to identify a numerical value, and an ordinal counter value indicative of the number of coverage events is determined based on the identified numerical value, less K.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 30, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Leonid Alexander Broukhis, Boris Gommershtadt, Florent Duru, Gabriel Gouvine, Dmitry Korchemny
  • Patent number: 10621296
    Abstract: A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: April 14, 2020
    Assignee: Synopsys, Inc.
    Inventors: Boris Gommershtadt, Alexander John Wakefield, Solaiman Rahim, Lakshmi Narayana Koduri Hanumath Prasad
  • Patent number: 10579760
    Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 3, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Ionut Silviu Cirjan, Boris Gommershtadt, Dmitry Korchemny, Naphtali Yehoshua Sprei
  • Publication number: 20200034499
    Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.
    Type: Application
    Filed: October 29, 2018
    Publication date: January 30, 2020
    Inventors: Ionut Silviu Cirjan, Boris Gommershtadt, Dmitry Korchemny, Naphtali Yehoshua Sprei
  • Patent number: 8214782
    Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: July 3, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt, Yael Duek-Golan
  • Patent number: 7886242
    Abstract: In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: February 8, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Swapnajit Chakraborti, Sandeep Pagey, Boris Gommershtadt, Yael Duek-Golan