Abstract: The present invention utilizes field programmable gate arrays (FPGAs) to implement a parallel differential quadrature phase shift keying (DQPSK) precoder and a DQPSK optical transmitter with an automatic realignment process. The present invention can perform DQPSK preceding, modulation, and data stream realignment at any lower rate, and its upper rate is determined by capability in speed and logic resources and external connections of available integrated circuit technology.

Abstract: DQPSK modulator control is provided using a single monitor photodiode with a selectively injected dither tone. The dither tone signal is sequentially injected into arm modulators and/or to a modulator driver port in time slots. A tapped signal at the output of the modulator is monitored synchronously with injected dither (I arm, Q arm, or phase modulator in third slot). The recovered dither output from a single photodiode is processed in the same sequence as the dither injection to adjust the bias to the optimal point: I-arm at the null point, Q-arm at the null point, and phase modulator at the quadrature point. This technique can be used for any control where the rate of change of the monitored condition due to systemic or environmental conditions (e.g., temperature, aging, etc.) is slow enough to allow time slot dither injection, monitor, and control.

Abstract: The present invention provides systems and methods for chirp control of a dual arm Z-modulator to minimize dispersion in the fiber plant. The chirp control is based upon a real-time control loop based upon performance monitoring data between a transmitter and a receiver. Advantageously, the present invention enables improved performance in high-speed optical systems, and in some cases can eliminate or minimize the need for external dispersion compensation fiber (DCF).

Abstract: RZ-DQPSK (Return-to-Zero Differential Quadrature Phase Shift Keying) systems and methods are provided with a single real-time phase alignment mechanism. The present invention eliminates the requirement for phase adjustment between a carver modulator and a DQPSK modulator. In an exemplary embodiment, the present invention replaces the carver modulator with AND gates between drivers of a DQPSK modulator and a data processor. The AND gates are configured to provide a single phase alignment signal.

Abstract: The present invention provides systems and methods for chirp control of a dual arm Z-modulator to minimize dispersion in the fiber plant. The chirp control is based upon a real-time control loop based upon performance monitoring data between a transmitter and a receiver. Advantageously, the present invention enables improved performance in high-speed optical systems, and in some cases can eliminate or minimize the need for external dispersion compensation fiber (DCF).

Abstract: The present invention provides systems and methods for chirp control of a dual arm Z-modulator to minimize dispersion in the fiber plant. The chirp control is based upon a real-time control loop based upon performance monitoring data between a transmitter and a receiver. Advantageously, the present invention enables improved performance in high-speed optical systems, and in some cases can eliminate or minimize the need for external dispersion compensation fiber (DCF).

Abstract: DQPSK modulator control is provided using a single monitor photodiode with a selectively injected dither tone. The dither tone signal is sequentially injected into arm modulators and/or to a modulator driver port in time slots. A tapped signal at the output of the modulator is monitored synchronously with injected dither (I arm, Q arm, or phase modulator in third slot). The recovered dither output from a single photodiode is processed in the same sequence as the dither injection to adjust the bias to the optimal point: I-arm at the null point, Q-arm at the null point, and phase modulator at the quadrature point. This technique can be used for any control where the rate of change of the monitored condition due to systemic or environmental conditions (e.g., temperature, aging, etc.) is slow enough to allow time slot dither injection, monitor, and control.

Abstract: RZ-DQPSK (Return-to-Zero Differential Quadrature Phase Shift Keying) systems and methods are provided with a single real-time phase alignment mechanism. The present invention eliminates the requirement for phase adjustment between a carver modulator and a DQPSK modulator. In an exemplary embodiment, the present invention replaces the carver modulator with AND gates between drivers of a DQPSK modulator and a data processor. The AND gates are configured to provide a single phase alignment signal.

Abstract: The present invention utilizes field programmable gate arrays (FPGAs) to implement a parallel differential quadrature phase shift keying (DQPSK) precoder and a DQPSK optical transmitter with an automatic realignment process. The present invention can perform DQPSK preceding, modulation, and data stream realignment at any lower rate, and its upper rate is determined by capability in speed and logic resources and external connections of available integrated circuit technology.

Abstract: The present invention provides systems and methods for chirp control of a dual arm Z-modulator to minimize dispersion in the fiber plant. The chirp control is based upon a real-time control loop based upon performance monitoring data between a transmitter and a receiver. Advantageously, the present invention enables improved performance in high-speed optical systems, and in some cases can eliminate or minimize the need for external dispersion compensation fiber (DCF).

Abstract: The present invention provides methods and systems for multiplexing five channels, such as 10 Gb/s to 50 Gb/s, into a single data sequence using a 5:1 multiplexer using a ?th ratio duty cycle clock. The ?th ratio duty cycle clock is a clock with a period equal to the channel data rate, and a pulse width equal to the period of data rate five times higher. The ?th ratio duty clock is combined with a proper combination of delays and phase shifters to allow the use of AND gates and OR gates to combine the five channels in a proper sequence to create a serial five-times higher data sequence.

Abstract: The present invention provides methods and systems for multiplexing five channels, such as 10 Gb/s to 50 Gb/s, into a single data sequence using a 5:1 multiplexer using a 1/5th ratio duty cycle clock. The 1/5th ratio duty cycle clock is a clock with a period equal to the channel data rate, and a pulse width equal to the period of data rate five times higher. The 1/5th ratio duty clock is combined with a proper combination of delays and phase shifters to allow the use of AND gates and OR gates to combine the five channels in a proper sequence to create a serial five-times higher data sequence.