Patents by Inventor Boris Levant

Boris Levant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260110975
    Abstract: Semiconductor device metrology including creating a time-domain representation of wavelength-domain measurement data of light reflected by a patterned structure of a semiconductor device, selecting an earlier-in-time portion of the time-domain representation that excludes a later-in-time portion of the time-domain representation, and determining one or more measurements of one or more parameters of interest of the patterned structure by performing model-based processing using the earlier-in-time portion of the time-domain representation.
    Type: Application
    Filed: August 4, 2025
    Publication date: April 23, 2026
    Applicant: NOVA LTD.
    Inventors: Gilad Barak, Michael Chemama, Smadar Ferber, Yanir HAINICK, Boris LEVANT, Ze'ev Lindenfeld, Dror SHAFIR, Yuri SHIRMAN, Elad Schleifer
  • Publication number: 20260094310
    Abstract: The presently disclosed subject matter includes a computer system and a computer-implemented method of generating synthetic examination output images, including synthetic fault images and synthetic fault-free images. The synthetic fault images comprise artificially generated 3D defects. The proposed technique enables fast, accurate, and efficient generation of a large and diverse collection of synthetic fault images and fault-free images, which can be implemented in runtime, as part of the examination process of semiconductor specimens.
    Type: Application
    Filed: September 30, 2024
    Publication date: April 2, 2026
    Inventors: Boris SHERMAN, Boris LEVANT, Ran BADANES, Ran YACOBY, Bar DUBOVSKI, Tomer YEMINY
  • Publication number: 20260087612
    Abstract: The presently disclosed subject matter includes a computer system and a computer-implemented method of generating synthetic examination output images, including synthetic fault images and synthetic fault-free images. The synthetic images comprise artificially generated 3D defects. A machine learning model is trained for transforming examination output images to height maps. The height maps are modified to include certain 3D features, and a second machine learning model is used for transforming the height maps to modified examination output images to exhibit the 3D features.
    Type: Application
    Filed: September 23, 2024
    Publication date: March 26, 2026
    Inventors: Boris SHERMAN, Boris LEVANT, Ran BADANES, Bar DUBOVSKI, Tomer YEMINY, Ran YACOBY
  • Publication number: 20260082866
    Abstract: The presently disclosed subject matter includes a method and a computer system dedicated for determining semiconductor specimen topography based on grayscale level (GL) imaging output. According to the disclosed approach, the semiconductor specimen surface is scanned from top-view using an examination tool such as a Scanning Electron Microscopy (SEM) to generate a grayscale level (GL) output image of the scanned surface. The GL output images are processed to deduce the corresponding height values of the scanned semiconductor specimen based on graphical features of the GL output images. The height values are then used for validating CMP hotspot predictions, which enhance the accuracy of hotspot detection and increase the reliability of the dummy fill results.
    Type: Application
    Filed: September 17, 2024
    Publication date: March 19, 2026
    Inventors: Michael SHIFRIN, Boris LEVANT, Vadim KUCHIK, Yorick TROUILLER, Aner AVAKRAT, Ran YACOBY
  • Patent number: 12573024
    Abstract: There is provided a system and method for defect examination on a semiconductor specimen. The method comprises obtaining an original image of the semiconductor specimen, the original image having a first region annotated as enclosing a defective feature; specifying a second region in the original image containing the first region, giving rise to a contextual region between the first region and the second region; identifying in a target image of the specimen a set of candidate areas matching the contextual region in accordance with a matching measure; selecting one or more candidate areas from the set of candidate areas; and pasting the first region or part thereof with respect to the one or more candidate areas, giving rise to an augmented target image usable for defect examination on the semiconductor specimen.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: March 10, 2026
    Assignee: Applied Materials Israel Ltd.
    Inventors: Boris Sherman, Boris Levant, Ran Yacoby, Botser Reshef, Tomer Yeminy
  • Patent number: 12561793
    Abstract: There is provided a system and method of examination of semiconductor specimens. The method includes generating a sequence of anomaly scores corresponding to a sequence of specimens sequentially fabricated and examined during a fabrication process, comprising, for each given specimen: obtaining an image of the given specimen acquired by an examination tool; using a machine learning (ML) model to process the image and obtaining an anomaly map indicative of pattern variation in the image; and deriving, based on the anomaly map, an anomaly score indicative of level of pattern variation presented in the given specimen, wherein the anomaly score is correlated with a defectivity score related to defect detection in a correlation relationship, and has higher detection sensitivity than the defectivity score; and analyzing the sequence of anomaly scores to monitor on-going process stability, thereby providing defect related prediction along the fabrication process based on the correlation relationship.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: February 24, 2026
    Assignee: Applied Materials Israel Ltd.
    Inventors: Noam Tal, Boris Levant, Sergey Sinitsa, Boaz Sturlesi, Shay Yogev, Assaf Ariel, Lilach Choona, Shaul Pres
  • Publication number: 20260024186
    Abstract: There are provided systems and methods comprising obtaining data Dpixel_intensity informative of a pixel intensity profile of a given specimen, feeding the data Dpixel_intensity to a machine learning model to determine, based on the data Dpixel_intensity, data informative of a depth of the given specimen, wherein the machine learning model has been trained with a training set, wherein at least part of the training set has been generated based on a model operative to predict, based on one or more parameters informative of a specimen, data informative of a pixel intensity profile of the specimen.
    Type: Application
    Filed: July 22, 2024
    Publication date: January 22, 2026
    Inventors: Vadim KUCHIK, Itay ASSULIN, Boris LEVANT, Ran YACOBY, Ran ITAY
  • Patent number: 12489020
    Abstract: There is provided a system and method for examining a semiconductor specimen. The method includes obtaining a runtime image of the specimen, and providing the runtime image as an input to an end-to-end (E2E) learning model to process, thereby obtaining, as an output of the E2E learning model, runtime measurement data specific for a metrology application. The E2E learning model is previously trained for the metrology application using a training set comprising a plurality of training images of the specimen and respective ground truth measurement data associated therewith, and one or more cost functions specifically configured to evaluate, for the plurality of training images and corresponding training measurement data outputted by the E2E learning model, one or more metrology benchmarks from a group comprising precision, correlation, and matching.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: December 2, 2025
    Assignee: Applied Materials Israel Ltd.
    Inventors: Tomer Haim Peled, Bar Dubovski, Noam Tal, Bobin Mathew Skaria, Boris Levant, Tal Frank
  • Patent number: 12469124
    Abstract: There is provided a system and method of examination of a semiconductor specimen. The method includes obtaining an e-beam image representative of a given layer of a given structure on the specimen in runtime, processing at least the e-beam image using a ML model, and obtaining yield related prediction with respect to the given structure prior to performing an electrical test. The ML model is previously trained using a training set comprising multiple stacks of e-beam images corresponding to multiple sites of the given structure on one or more training specimens, each stack of e-beam images representative of the at least given layer of a respective site; and test data acquired from an electrical test performed at the multiple sites and related to actual yield of the training specimens, the test data respectively correlated with the stacks of e-beam images and used as ground truth thereof.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: November 11, 2025
    Assignee: Applied Materials Israel Ltd.
    Inventors: Boris Levant, Noam Tal, Ran Yacoby, Lilach Choona, Shaul Pres, Jasmin Sonia Linshiz, Shay Yogev, Assaf Ariel
  • Patent number: 12214601
    Abstract: A method includes, receiving a first digital image (FDI) to-be printed by a digital printing system (DPS) (10). In a in training phase: for first selected regions (111) in the FDI, a first set of synthetic images (SIs) (112A, 112B, 114A, 114B, 116A, 116B) having a defect caused by a defective part (DP) (99) in the first selected regions, is produced; a neural network (NN) (150) is trained to detect the defect using the first set SIs. In a subsequent detection phase: the NN is applied for identifying, in a second digital image (SDI) (136, 146) acquired from an image produced by the DPS, suspected second regions (135, 145); for each of the second regions, a second set (137, 147) of SIs having DPs that form the defects, is produced; and the DP is identified by comparing, in each of the second regions, between the SDI and the second set SIs.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 4, 2025
    Assignee: Landa Corporation Ltd.
    Inventors: Boris Levant, Shai Silberstein, Tomer Yanir, Avraham Guttman, Alon Siman Tov
  • Publication number: 20240428396
    Abstract: There is provided a system and method of semiconductor specimen examination. The method includes obtaining a plurality of images of a semiconductor specimen acquired by an examination tool; processing the plurality of images using a first machine learning (ML) model for defect detection, thereby obtaining, from the plurality of images, a set of images labeled with detected defects, wherein the first ML model is previously trained using a first training set comprising a subset of synthetic defective images each containing one or more synthetic defects, and a subset of nominal images; and training a second ML model using a second training set comprising at least part of the set of images labeled with detected defects, wherein the second ML model, upon being trained, is usable for defect detection with improved detection performance with respect to the first ML model.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: Boris SHERMAN, Boris LEVANT, Ran YACOBY, Bar DUBOVSKI, Botser RESHEF, Tomer YEMINY, Omer GRANOVITER, Ran BADANES
  • Publication number: 20240289940
    Abstract: There are provided systems and methods comprising, for each given overlay target of a plurality of different overlay targets to be manufactured on a semiconductor specimen, said given overlay target comprising a plurality of stacked semiconductor layers, obtaining a design image of the given overlay target, feeding the design image to a trained machine learning model, to simulate at least one image of the given overlay target that would have been acquired by an electron beam examination system, using the at least one image to determine, before actual manufacturing of the given overlay target, data informative of at least one simulated overlay in the image, and using the data informative of the at least one simulated overlay of each given overlay target to select at least one optimal overlay target among the plurality of different overlay targets, the optimal overlay target being usable to be manufactured on the semiconductor specimen.
    Type: Application
    Filed: February 21, 2024
    Publication date: August 29, 2024
    Inventors: Bar DUBOVSKI, Ran YACOBY, Tung-Yuan HSIEH, Kevin Ryan HOUCHENS, Tal ITZKOVICH, Nahum BOMSHTEIN, Jenny PERRY, Boris LEVANT
  • Publication number: 20240281956
    Abstract: There is provided a system and method of examination of semiconductor specimens. The method includes generating a sequence of anomaly scores corresponding to a sequence of specimens sequentially fabricated and examined during a fabrication process, comprising, for each given specimen: obtaining an image of the given specimen acquired by an examination tool; using a machine learning (ML) model to process the image and obtaining an anomaly map indicative of pattern variation in the image; and deriving, based on the anomaly map, an anomaly score indicative of level of pattern variation presented in the given specimen, wherein the anomaly score is correlated with a defectivity score related to defect detection in a correlation relationship, and has higher detection sensitivity than the defectivity score; and analyzing the sequence of anomaly scores to monitor on-going process stability, thereby providing defect related prediction along the fabrication process based on the correlation relationship.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Noam TAL, Boris LEVANT, Sergey SINITSA, Boaz STURLESI, Shay YOGEV, Assaf ARIEL, Lilach CHOONA, Shaul PRES
  • Publication number: 20240281958
    Abstract: There is provided a system and method of examination of a semiconductor specimen. The method includes obtaining an e-beam image representative of a given layer of a given structure on the specimen in runtime, processing at least the e-beam image using a ML model, and obtaining yield related prediction with respect to the given structure prior to performing an electrical test. The ML model is previously trained using a training set comprising multiple stacks of e-beam images corresponding to multiple sites of the given structure on one or more training specimens, each stack of e-beam images representative of the at least given layer of a respective site; and test data acquired from an electrical test performed at the multiple sites and related to actual yield of the training specimens, the test data respectively correlated with the stacks of e-beam images and used as ground truth thereof.
    Type: Application
    Filed: February 22, 2023
    Publication date: August 22, 2024
    Inventors: Boris LEVANT, Noam TAL, Ran YACOBY, Lilach CHOONA, Shaul PRES, Jasmin Sonia LINSHIZ, Shay YOGEV, Assaf ARIEL
  • Publication number: 20240105522
    Abstract: There is provided a system and method for examining a semiconductor specimen. The method includes obtaining a runtime image of the specimen, and providing the runtime image as an input to an end-to-end (E2E) learning model to process, thereby obtaining, as an output of the E2E learning model, runtime measurement data specific for a metrology application. The E2E learning model is previously trained for the metrology application using a training set comprising a plurality of training images of the specimen and respective ground truth measurement data associated therewith, and one or more cost functions specifically configured to evaluate, for the plurality of training images and corresponding training measurement data outputted by the E2E learning model, one or more metrology benchmarks from a group comprising precision, correlation, and matching.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 28, 2024
    Inventors: Tomer Haim PELED, Bar DUBOVSKI, Noam TAL, Bobin Mathew SKARIA, Boris LEVANT, Tal FRANK
  • Publication number: 20240095903
    Abstract: There is provided a system and method for defect examination on a semiconductor specimen. The method comprises obtaining an original image of the semiconductor specimen, the original image having a first region annotated as enclosing a defective feature; specifying a second region in the original image containing the first region, giving rise to a contextual region between the first region and the second region; identifying in a target image of the specimen a set of candidate areas matching the contextual region in accordance with a matching measure; selecting one or more candidate areas from the set of candidate areas; and pasting the first region or part thereof with respect to the one or more candidate areas, giving rise to an augmented target image usable for defect examination on the semiconductor specimen.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Inventors: Boris SHERMAN, Boris LEVANT, Ran YACOBY, Botser RESHEF, Tomer YEMINY
  • Publication number: 20230264483
    Abstract: A method includes, receiving a first digital image (FDI) to-be printed by a digital printing system (DPS) (10). In a in training phase: for first selected regions (111) in the FDI, a first set of synthetic images (SIs) (112A, 112B, 114A, 114B, 116A, 116B) having a defect caused by a defective part (DP) (99) in the first selected regions, is produced; a neural network (NN) (150) is trained to detect the defect using the first set SIs. In a subsequent detection phase: the NN is applied for identifying, in a second digital image (SDI) (136, 146) acquired from an image produced by the DPS, suspected second regions (135, 145); for each of the second regions, a second set (137, 147) of SIs having DPs that form the defects, is produced; and the DP is identified by comparing, in each of the second regions, between the SDI and the second set SIs.
    Type: Application
    Filed: May 12, 2021
    Publication date: August 24, 2023
    Inventors: Boris Levant, Shai Silberstein, Tomer Yanir, Avraham Guttman, Alon Siman Tov
  • Patent number: 11630618
    Abstract: A method for correcting an error in image printing, the method includes receiving a reference digital image (RDI). Based on a predefined selection criterion, one or more regions in the RDI that are suitable for use as anchor features for sensing the error, are automatically selected. A digital image (DI) acquired from a printed image of the RDI, is received and the one or more regions are automatically identified in the DI. Based on the anchor features of the DI, the error is automatically estimated in the printed image. A correction that, when applied to the DI, compensates for the estimated error, is calculated. The estimated error is corrected in a subsequent digital image (SDI) to be printed, and the SDI having the corrected error, is printed.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: April 18, 2023
    Assignee: LANDA CORPORATION LTD.
    Inventor: Boris Levant
  • Publication number: 20220390858
    Abstract: Semiconductor device metrology including creating a time-domain representation of wavelength-domain measurement data of light reflected by a patterned structure of a semiconductor device, selecting an earlier-in-time portion of the time-domain representation that excludes a later-in-time portion of the time-domain representation, and determining one or more measurements of one or more parameters of interest of the patterned structure by performing model-based processing using the earlier-in-time portion of the time-domain representation.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 8, 2022
    Inventors: GILAD BARAK, MICHAEL CHEMAMA, SMADAR FERBER, YANIR HAINICK, BORIS LEVANT, ZE'EV LINDENFELD, DROR SHAFIR, YURI SHIRMAN, ELAD SCHLEIFER
  • Patent number: 11366398
    Abstract: Semiconductor device metrology including creating a time-domain representation of wavelength-domain measurement data of light reflected by a patterned structure of a semiconductor device, selecting an earlier-in-time portion of the time-domain representation that excludes a later-in-time portion of the time-domain representation, and determining one or more measurements of one or more parameters of interest of the patterned structure by performing model-based processing using the earlier-in-time portion of the time-domain representation.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 21, 2022
    Assignee: NOVA LTD
    Inventors: Gilad Barak, Michael Chemama, Smadar Ferber, Yanir Hainick, Boris Levant, Ze'Ev Lindenfeld, Dror Shafir, Yuri Shirman, Elad Schleifer