Abstract: Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology into an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.

Abstract: Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including a plurality of operational amplifiers and a plurality of resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection. The method also includes generating a resistance matrix for the weight matrix. Each element of the resistance matrix corresponds to a respective weight of the weight matrix and represents a resistance value.

Abstract: Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes calculating one or more connection constraints based on analog integrated circuit (IC) design constraints. The method also includes transforming the neural network topology to an equivalent sparsely connected network of analog components satisfying the one or more connection constraints. The method also includes computing a weight matrix for the equivalent sparsely connected network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent sparsely connected network.

Abstract: Systems, devices, integrated circuits, and methods are provided for analog hardware realization of neural networks. An electronic device includes a plurality of resistors corresponding to a plurality of weights of a neural network and one or more amplifiers coupled to the plurality of resistors. The plurality of resistors includes a first resistor corresponding to a first weight of the neural network. The one or more amplifiers and the plurality of resistors are configured to form a neural network circuit associated with the neural network. In some embodiments, the electronic device includes a combination circuit corresponding to a neuron of the neural network and configured to: (i) obtain two or more input signals at the two or more input interfaces, (ii) combine the two or more input signals, and (iii) generate an output.

Abstract: Electrochromic devices and components thereof and systems and methods for controlling electrochromic devices are disclosed. Further, electrochromic materials, electrochromic compositions and electrochromic layers useful for the devices and systems can be in the form of a gel. The present disclosure also provide methods to fabricate electrochromic devices and components thereof, electrochromic compositions, layers and gels.

Abstract: Systems, devices, integrated circuits, and methods are provided for analog hardware realization of neural networks. An electronic device includes a plurality of resistors corresponding to a plurality of weights of a neural network and one or more amplifiers coupled to the plurality of resistors. The plurality of resistors includes a first resistor corresponding to a first weight of the neural network. The one or more amplifiers and the plurality of resistors are configured to form a neural network circuit associated with the neural network. The first resistor has a variable resistance. In some embodiments, the first resistor is formed based on a crossbar array of resistive elements or a crossbar array of memory cells. Each resistive element or memory cell is located at a cross point of, and electrically coupled between, a respective word line and a respective bit line.

Abstract: Systems and methods are provided for optimizing energy efficiency of analog neuromorphic circuits. The method includes obtaining an integrated circuit implementing an analog network of analog components including operational amplifiers and resistors. The analog network represents a trained neural network, each operational amplifier represents an analog neuron, and each resistor represents a connection between two analog neurons. The method also includes generating inferences using the integrated circuit for test inputs, including simultaneously transferring signals from one layer to a subsequent layer. The method also includes, while generating inferences: in accordance with a determination that a level of signal output of the operational amplifiers is equilibrated: determining an active set of analog neurons of the analog network influencing signal formation for propagation of signals; and turning off power for other analog neurons of the analog network, for a predetermined period of time.

Abstract: Systems, devices, integrated circuits, and methods are directed to on-vehicle data processing using analog hardware realization of neural networks. A vehicle obtains a temporal sequence of sensor data samples that is collected by a sensor system including a tire pressure sensor and/or a three-axis accelerometer. The sensor system is physically coupled to a tire of a vehicle. The temporal sequence of sensor data samples is converted into a plurality of first parallel data items, which is applied as a plurality of first inputs to a neural network circuit. The neural network circuit generates one or more output data items based on the plurality of first parallel data items. The one or more output data items indicate a condition of the road, the vehicle, or a component of the vehicle.

Abstract: Systems, devices, integrated circuits, and methods are directed to on-vehicle data processing using analog hardware realization of neural networks. A vehicle obtains a temporal sequence of sensor data that is collected by a microphone of a sensor system. The sensor system is physically coupled to a tire of a vehicle. The neural network circuit generates one or more output data items based on the sensor data, and the one or more output data items indicate the condition of a road, the vehicle, or a component of the vehicle. The sensor system, including an electronic device that includes the microphone, is also described herein. A method of training the neural network is also described herein.

Abstract: Electrochromic devices and components thereof and systems and methods for controlling electrochromic devices are disclosed. Further, electrochromic materials, electrochromic compositions and electrochromic layers useful for the devices and systems can be in the form of a gel. The present disclosure also provide methods to fabricate electrochromic devices and components thereof, electrochromic compositions, layers and gels.

Abstract: Systems, devices, integrated circuits, and methods are provided for layer-based analog hardware realization of neural networks. An electronic device includes a collection of resistors, a collection of amplifiers, and a controller. The controller is configured to implement each of the plurality of layers sequentially. For each of the plurality of layers, the controller extracts, from memory, a plurality of layer parameters corresponding to a plurality of weights of the respective layer, and in accordance with the plurality of layer parameters, selects a plurality of resistors and a plurality of amplifiers and forms a set of input resistors from the plurality of resistors. The set of input resistors are electrically coupled to the plurality of amplifiers to form a neural layer circuit. The neural layer circuit may obtain a plurality of input signals via the plurality of resistors and generate a plurality of output signals from the plurality of input signals.

Abstract: Systems and methods are provided for sound signal processing using neuromorphic analog signal processors. A hardware apparatus includes a digital switch coupled to a plurality of analog neuromorphic cores. The digital switch is configured to obtain one or more sound streams from one or more sound sources, transmit data based on the one or more sound streams to the plurality of analog neuromorphic cores, receive output from the plurality of analog neuromorphic cores, and output one or more modified sound streams based on the output received from the plurality of analog neuromorphic cores. Each analog neuromorphic core includes a respective analog network of analog components and is configured to (i) receive respective input data from the digital switch, (ii) perform a respective voice-related function on the respective input data, and (iii) transmit respective output to the digital switch.

Abstract: An integrated circuit includes an analog network of analog components fabricated by a method. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including operational amplifiers and resistors. Each operational amplifier represents an analog neuron, and each resistor represents a connection between analog neurons. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. The method also includes generating a resistance matrix for the weight matrix. The method also includes generating lithographic masks for fabricating a circuit implementing the equivalent analog network based on the resistance matrix. The method also includes fabricating the circuit based on the one or more lithographic masks using a lithographic process.

Abstract: Systems and methods are provided for analog hardware realization of neural networks. The method includes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology to an equivalent analog network of analog components including operational amplifiers and resistors. Each operational amplifier represents an analog neuron of the equivalent analog network, and each resistor represents a connection between two analog neurons. The method also includes computing a weight matrix based on the weights of the trained neural network. The method also includes generating a resistance matrix for the weight matrix. The method also includes pruning the equivalent analog network to reduce the number of operational amplifiers or the resistors, based on the resistance matrix, to obtain an optimized analog network of analog components.

Abstract: The various implementations described herein include methods for improving signal-to-noise ratios of analog circuit implementations of neural networks. In one aspect, a method includes quantizing weights of a trained neural network to form a quantized neural network having a quantized output neuron in a final nth layer. The method also includes forming a second neural network having: n+1 layers; layers 1, . . . , n?1 identical to respective layers 1, . . . , n?1 of the trained neural network; an nth layer that includes a plurality of neurons identical to the output neuron; and an (n+1)th layer that includes one neuron that computes the average from the plurality of neurons in the nth layer. The method further includes transforming the quantized second neural network into an analog network by computing a weight matrix for the analog network, and generating a schematic for the analog network.

Abstract: Systems, devices, integrated circuits, and methods are provided for analog hardware realization of neural networks. An electronic device includes a plurality of resistors corresponding to a plurality of weights of a neural network and one or more amplifiers coupled to the plurality of resistors. The plurality of resistors includes a first resistor corresponding to a first weight of the neural network. The one or more amplifiers and the plurality of resistors are configured to form a neural network circuit associated with the neural network. The first resistor has a variable resistance. In some embodiments, the first resistor is formed based on a crossbar array of resistive elements or a crossbar array of memory cells. Each resistive element or memory cell is located at a cross point of, and electrically coupled between, a respective word line and a respective bit line.

Abstract: A method for hardware realization of neural networks executes at a computing device. The device obtains a neural network topology for a trained convolutional neural network that transforms a set of input tensors and generates a set of intermediate tensors. The device computes a measure of locality for tensors of the trained convolutional neural network based on dependencies between the set of input tensors and the set of intermediate tensors. The device transforms the trained convolutional neural network into an equivalent buffered neural network that includes a left subnetwork and a right subnetwork based on the neural network topology and the measure of locality. The left subnetwork and the right subnetwork are interconnected via a buffer. The device generates a schematic model for implementing the equivalent buffered neural network, including selecting component parameter values for neurons of the equivalent buffered neural network and connections between the neurons.

Abstract: A hardware apparatus implements a neural network. In some embodiments, the neural network is a trained convolutional neural network. The hardware apparatus includes a network of interconnected neurons (e.g., implemented in operational amplifiers and resistors). The network of interconnected neurons has a plurality of subnetworks, including a left subnetwork and a right subnetwork. The left and right subnetworks are interconnected via a buffer. The left subnetwork of neurons and the right subnetwork of neurons are configured to operate at different frequencies and/or the right subnetwork is configured to operate conditionally based on content of the buffer.

Abstract: An apparatus is provided for detonation control in spark ignition engines. The apparatus includes an analog neurocomputing hardware device, a knock sensor coupled to a spark ignition engine, an ignition coil for the spark ignition engine, and an Electronic Control Unit (ECU) for the spark ignition engine. The analog neuromorphic hardware device is configured to receive knock signals from the knock sensor, receive ignition coil data from the ignition coil, determine a knock level and ignition quality measure based on the received knock sensor signals and the received ignition coil data, and transmit the knock level and ignition quality measure to the ECU.

Abstract: Systems and methods are provided for analog hardware realization of neural networks. The method incudes obtaining a neural network topology and weights of a trained neural network. The method also includes transforming the neural network topology into an equivalent analog network of analog components. The method also includes computing a weight matrix for the equivalent analog network based on the weights of the trained neural network. Each element of the weight matrix represents a respective connection between analog components of the equivalent analog network. The method also includes generating a schematic model for implementing the equivalent analog network based on the weight matrix, including selecting component parameter values for the analog components.