Patents by Inventor Boris Ostrovsky

Boris Ostrovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7058743
    Abstract: A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: June 6, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Boris Ostrovsky, Christopher J. Jackson
  • Patent number: 6826671
    Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: November 30, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Boris Ostrovsky, Daniel R. Cassiday, John R. Feehrer, David A. Wood, Pazhani Pillai, Christopher J. Jackson, Mark Donald Hill
  • Publication number: 20040019723
    Abstract: A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 29, 2004
    Inventors: Boris Ostrovsky, Christopher J. Jackson
  • Publication number: 20030070058
    Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Inventors: Boris Ostrovsky, Daniel R. Cassiday, John R. Feehrer, David A. Wood, Pazhani Pillai, Christopher J. Jackson, Mark Donald Hill