Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.

Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.

Abstract: In an embodiment, an electronic component includes a dielectric layer having a first surface and a second surface, one or more semiconductor dies embedded in the dielectric layer and at least one electrically conductive member. The electrically conductive member includes a first portion and a second portion. The first portion includes a foil including a first metal and the second portion includes an electrodeposited layer including a second metal. The first portion and the second portion are embedded in the dielectric layer.

Abstract: A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract: A semiconductor component arrangement having a semiconductor component, a mount, and an adhesive, wherein the adhesive connects the semiconductor component to the mount and the adhesive contains a marker substance. Also disclosed is a method for inspecting the connection of a semiconductor component to a mount. The semiconductor component is fixed on the mount using an adhesive, wherein the adhesive contains a marker substance, the mount with the semiconductor component is cleaned, and the mount is inspected for residues of the adhesive on the basis of radiation which is characteristic of the marker substance.