Abstract: An adapter for a communications module includes first terminals for connection with a host interface of a given platform, and second terminals for connection with the communications module. The host interface provides signals associated with the platform and power at corresponding first terminals. The communication module provides associated signals and connections for supplying voltages to the module circuits, at corresponding second terminals. A power converter connected to the first terminals is arranged to output fixed voltages one or more of which is required for the communications module. A power management stage connected to the output of the power converter is arranged to apply the voltages to the second terminals so that the voltages are properly supplied to the module circuits. A buffer stage connected to the first and the second terminals is arranged to buffer or condition shared signals among the host interface and the communications module.

Abstract: A compact radio core engine (CE) module uniquely small in size and power consumption, in which only two circuit boards provide all the modem and transceiver functions needed for modern military radios. A modem circuit board has modem devices and a first connector mounted on the board, and a radio frequency (RF) circuit board has RF devices and a second connector mounted on the board. A module frame has an interior wall, and a side wall about the periphery of the interior wall. The modem and the RF circuit boards are positioned on opposite sides of the interior wall, and the connectors on the two boards mate with one another through an opening in the interior wall to exchange operating data and signals between the devices on the boards. The modem circuit board is seated entirely within a recess formed by the interior and the side walls of the frame.

Abstract: A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

Abstract: A system and method for allowing individual register access during system integration and test is disclosed. A Chip select is routed between an OMAP processor and a waveform FPGA and configured to allow individual register access during system integration and test. Logic is then added to the FPGA to support the single access to the FPGA's peripherals. This allows the user connected to the debug port to be able to send and receive individual commands to and from the waveform FPGA's peripherals. A Graphical User Interface (GUI) maybe developed to provide a graphical interface or scripts may be used to assemble multiple commands thereby increasing flexibility to configure the peripherals during integration and troubleshooting.

Abstract: A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at high frequency. In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at low rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.

Abstract: A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas.

Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.

Abstract: A system and method for connecting an advanced electronic module to a legacy chassis is presented. In one embodiment, a connector plate comprises a plate bracket, a module connector, at least two chassis connectors and route logic. The plate bracket has a front side, a back side and an opening. The module connector connects to an electronic module within the opening. The at least two chassis connectors are located on the back side of the bracket plate and are configured to be connected to a legacy chassis or and advanced chassis. The legacy chassis and the advanced chassis do not expect signals from the same number chassis conductors. The routing logic routes signals from the module connector to each of the at least two chassis connectors.

Abstract: An adapter for a communications module includes first terminals for connection with a host interface of a given platform, and second terminals for connection with the communications module. The host interface provides signals associated with the platform and power at corresponding first terminals. The communication module provides associated signals and connections for supplying voltages to the module circuits, at corresponding second terminals. A power converter connected to the first terminals is arranged to output fixed voltages one or more of which is required for the communications module. A power management stage connected to the output of the power converter is arranged to apply the voltages to the second terminals so that the voltages are properly supplied to the module circuits. A buffer stage connected to the first and the second terminals is arranged to buffer or condition shared signals among the host interface and the communications module.

Abstract: A system and method for allowing individual register access during system integration and test is disclosed. A Chip select is routed between an OMAP processor and a waveform FPGA and configured to allow individual register access during system integration and test. Logic is then added to the FPGA to support the single access to the FPGA's peripherals. This allows the user connected to the debug port to be able to send and receive individual commands to and from the waveform FPGA's peripherals. A Graphical User Interface (GUI) maybe developed to provide a graphical interface or scripts may be used to assemble multiple commands thereby increasing flexibility to configure the peripherals during integration and troubleshooting.

Abstract: A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at high frequency. In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at low rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.

Abstract: A method and apparatus of using DICE-T personality cards to adapt the incoming voltages supplied by the GVA and provide the ability to turn any voltage to any card on or off depending upon operating mode in a radio system is disclosed. The ability to control voltages individually also allows the control of the power-up sequencing of any card. The DICE-T personality cards use voltages from GVA to generate the additional voltages required by the Core Engines and VHF Module. All of the voltages are connected to hot-swap controllers which provide switching of the power to each destination. These hot-swap controllers also provide monitoring of voltage and shut-down if over-current conditions occur. The two DICE-T personality cards each have a Complex Programmable Logic Device (CPLD) controls the hot-swap controller for each voltage. The CPLD also controls the sequencing of the individual voltages applied to each module.

Abstract: A compact communications radio core engine (CE) module includes a modem circuit board having a first connector, and a radio frequency (RF) circuit board having a second connector configured to mate with the first connector of the modem circuit card. A module shell is constructed and arranged to contain the modem and the RF circuit boards in such an orientation so that the second connector of the RF circuit board can operatively engage the first connector of the modem circuit card.

Abstract: An expansion card and method for controlling a radio system integrates PCDD operations into a PCMCIA or ExpressCard which can be inserted into an external display, smart screen PCMCIA slot, or laptop ExpressCard or PCMCIA slot to allow an operator to control the radio system with a computer without any modification of the computer.

Abstract: A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

Abstract: A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas.