Abstract: According to some aspects, a network interoperability device is provided, comprising a first interface configured to electrically couple to one or more inter-integrated circuit (I2C) devices via an I2C bus, a second interface configured to electrically couple to a data input port and a distinct data output port of a non-I2C transceiver, and a control circuit electrically coupled to the first and second interfaces and configured to control communication of an I2C frame between the I2C bus and the non-I2C transceiver.

Abstract: According to some aspects, a network interoperability device is provided, comprising a first interface configured to electrically couple to one or more inter-integrated circuit (I2C) devices via an I2C bus, a second interface configured to electrically couple to a data input port and a distinct data output port of a non-I2C transceiver, and a control circuit electrically coupled to the first and second interfaces and configured to control communication of an I2C frame between the I2C bus and the non-I2C transceiver.

Abstract: Some embodiments are directed to cooling frames for mezzanine cards, mezzanine card assemblies and circuit card assemblies. A recessed cooling frame may be used to dissipate heat generated by components of a mezzanine card. The cooling frame may be directly coupled to a host card or host card cooling frame, thereby reducing the number of interfaces and reducing the thermal resistance of the heat dissipation pathway. The cooling frames of some embodiments may provide more efficient heat dissipation and thereby allow higher performance mezzanine cards to be used. Some embodiments provide a mezzanine card assembly that conforms to the mechanical envelope dimensions of the VITA 20, VITA 42 or VITA 61 specifications.

Abstract: Differential equalizers and systems, methods, and computer products thereof configured and operative to dynamically compensate for signal losses over a wide frequency range by maintaining a relatively constant or consistent differential potential over the frequency range are disclosed. Received signals can be dynamically scaled down based on their frequency content such that all of the signals are outputted at or around a relatively constant amplitude.

Abstract: Some embodiments are directed to cooling frames for mezzanine cards, mezzanine card assemblies and circuit card assemblies. A recessed cooling frame may be used to dissipate heat generated by components of a mezzanine card. The cooling frame may be directly coupled to a host card or host card cooling frame, thereby reducing the number of interfaces and reducing the thermal resistance of the heat dissipation pathway. The cooling frames of some embodiments may provide more efficient heat dissipation and thereby allow higher performance mezzanine cards to be used. Some embodiments provide a mezzanine card assembly that conforms to the mechanical envelope dimensions of the VITA 20, VITA 42 or VITA 61 specifications.

Abstract: Differential equalizers and systems, methods, and computer products thereof configured and operative to dynamically compensate for signal losses over a wide frequency range by maintaining a relatively constant or consistent differential potential over the frequency range are disclosed. Received signals can be dynamically scaled down based on their frequency content such that all of the signals are outputted at or around a relatively constant amplitude.

Abstract: The present invention features are series of techniques for designing and assembling of large, robust monolithic and monolithic-like flat panel displays. Many techniques originally developed for creating tiled, flat-panel displays having visually imperceptible seams may be advantageously applied to monolithic structures. These techniques include single-sided wiring, two-sided wiring from opposite sides, segmented row and column lines, and reordering row and column lines in fan-out region. Single-sided wiring facilitates the construction of displays with small outlines. By using these techniques, display sharpness and contrast may be improved. In addition, color and luminance balance and uniformity across the display may also be improved.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: The present invention features techniques for designing large, robust monolithic and monolithic-like displays having good brightness and contrast over a wide range of viewing angles. These techniques include controlling the layout of the pixel array and its access circuits that modify the electrical characteristics in order to minimize undesirable optical, electro-optical, and ambient light aberrations and any electronic anomalies creating visually perceptible discontinuities or boundaries. These artifacts are reduced to levels that allow for better color correction. In addition, the use of optical components such as collimators, light enhancing films, diffusers, screens, polarizers and masks are described. The resulting displays present luminance and chromaticity outputs from areas of originally varying optical response that become uniform within the tolerances of the human visual system.

Abstract: The present invention features are series of techniques for designing and assembling of large, robust monolithic and monolithic-like flat panel displays. Many techniques originally developed for creating tiled, flat-panel displays having visually imperceptible seams may be advantageously applied to monolithic structures. These techniques include single-sided wiring, two-sided wiring from opposite sides, segmented row and column lines, and reordering row and column lines in fan-out region. Single-sided wiring facilitates the construction of displays with small outlines. By using these techniques, display sharpness and contrast may be improved. In addition, color and luminance balance and uniformity across the display may also be improved.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: The present invention features are series of techniques for designing and assembling of large, robust monolithic and monolithic-like flat panel displays. Many techniques originally developed for creating tiled, flat-panel displays having visually imperceptible seams may be advantageously applied to monolithic structures. These techniques include single-sided wiring, two-sided wiring from opposite sides, segmented row and column lines, and reordering row and column lines in fan-out region. Single-sided wiring facilitates the construction of displays with small outlines. By using these techniques, display sharpness and contrast may be improved. In addition, color and luminance balance and uniformity across the display may also be improved.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: The present invention features are series of techniques for designing and assembling of large, robust monolithic and monolithic-like flat panel displays. Many techniques originally developed for creating tiled, flat-panel displays having visually imperceptible seams may be advantageously applied to monolithic structures. These techniques include single-sided wiring, two-sided wiring from opposite sides, segmented row and column lines, and reordering row and column lines in fan-out region. Single-sided wiring facilitates the construction of displays with small outlines. By using these techniques, display sharpness and contrast may be improved. In addition, color and luminance balance and uniformity across the display may also be improved.

Abstract: The present invention features designs of pixels and designs of control features for seals on AMLCD tiles optimized for tiling AMLCD flat panel displays (FPDs) which have visually imperceptible seams. The FPD structure has an image view plane which is continuous and remote from the pixel apertures or image source plane on the inside of the tiles. The image is formed on the view plane by a distributed ultra low magnification flies-eye optical system (a screen) that is integrated with the tiles, effectively excluding and obscuring an image of the seams. The innovations described herein minimize the defects on the perimeter pixels by effectively damming the waviness of the front of the seal near the perimeter pixels on the tiles. Dark space required for the seal between the interior tile edges and active regions of the pixels is decreased, as is the space allocated for wiring thereby increasing the feasible aperture ratios near the mosaic edges and all apertures.

Abstract: The present invention features a tiled, flat-panel, color display that has a color-correction capability. The display is a tiled mosaic of individual display tiles, such as AMLCDs. Column and row inputs that are typically provided for a single display tile system are distributed over a plurality of display tiles. The color purity is achieved for the display by sorting the tiles into groups, matching their color coordinates, and correcting non-uniformities optically (e.g., by using a graded neutral density filter having a grading function being the inverse of the brightness distribution non-uniformities) and/or electronically. Then, each individual tile in the mosaic is color-corrected via a multiplexed, controller/driver circuit.

Abstract: The present invention features methods and apparatus for the correction of spatial non-uniformities in brightness that arise from materials, manufacturing, operational and lighting parameter variations in electronic color, flat-panel displays. The methods apply both to gradual non-uniformities usually found in monolithic displays as well as to abrupt variations present in displays composed of a multitude of tiles. Corrections are performed on the electronic drive signals used to control the brightness of selected display pixels. Parameters required for these corrections are acquired via brightness measurements over selected pixels and stored after suitable transformations. The stored parameters are then used to scale and/or interpolate drive signals in real time. Corrections are performed such that any remaining gradual and abrupt brightness non-uniformities fall below the detectable threshold under the intended viewing conditions.

Abstract: The present invention features flat-panel displays having a mosaic of tiles, and methods of constructing and sealing them. Sealing designs are described to maintain appropriate vacuum levels for FEDs, PFPDs and LCDs. The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure positioned between them; these are known as s-tiles. The tiles may be enclosed by a cover plate and backplate. Non-permeable material may be deposited on the cover plate and the backplate, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also located between the cover plate and backplate for hermetically sealing the perimeter of the display. A set of electrical-interconnection, metal feed-throughs can also be positioned in the non-permeable spacer/connector.

Abstract: The present invention features methods and apparatus for the correction of spatial non-uniformities in color only, and color and brightness combined, that arise from materials, manufacturing, and operational variations in tiled, color flat-panel displays. Such uniformities can introduce gradual or abrupt color and brightness variations in monolithic and tiled displays. Correction methods are based on control of the manufacturing and assembly process, and/or remapping of the colors of the display to match uniformity requirements of the average human observer. Correction methods can be implemented using serial and parallel versions using electronic circuits commonly used in video signal processing. Apparatus for a self-calibration method are also described.