Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).

Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).

Abstract: Method for generating and thereafter updating a data structure used for routing Internet protocol data packets. Routing a packet is performed by using a destination address of the packet and an updatable set of prefix rules. A prefix rule may be added to a first-level table if the terminating level of the prefix rule equals one. Otherwise, cascading tables may be created until reaching a terminating table for the prefix rule. Then, the prefix rule may be added to its terminating table. The data structure is updateable. The packet routing may be guided by associating one or more fields, or partial fields, of the most significant bits of a destination address of the packet with respective records of search tables, and using the last visited port identifier for routing there through the packet. The data structure is generated by a control processor and stored in a system memory, whereas a network processor searches in the data structure for a prefix rule suitable for each received packet.

Abstract: The present invention provides techniques for efficiently determining a minimum or maximum of a plurality of values and the index of the minimum using registers of a processor. The present invention also provides for various processor instructions for determining the minimum/maximum and index of two or more values. The present invention finds particular benefit in implementing heaps and in systems utilizing Weighted Fair Queuing (WFQ).

Abstract: A system and method for communicating messages between tasks on separate processors in a multiprocessor system are disclosed herein. A mediator task having a separate incoming message queue is used to handle message(s) from remote task(s) on other processor(s). A message from a remote task intended for a local task of a local processor is stored in the message queue of the mediator task. During an execution of the mediator task on the local processor, the mediator task is adapted to transfer the message from its message queue to the message queue of the intended local task, either directly or via another task. The present invention finds particular benefit in data processing in network devices.

Abstract: A method and a device for translating a hierarchical address, the device is adapted to receive a destination address, to search an array of sorted binary string being associated with a group of addresses reachable through the device, and to provide a best matching address, the device comprising: a content addressable memory module, for storing a first portion of the array of sorted binary strings; a fast memory module, for storing a second portion of the sorted binary strings; a memory module, for storing a remaining portion of the tree of sorted strings; and a search engine, coupled to the content addressable memory unit module, the fast memory module and the memory module, configured to receive a destination address, access at least the fast memory unit and the memory unit and to find the best matching address.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: A system and method for performing longest prefix matching processing, such as that employed for IP destination address lookups, is disclosed. The technique, referred as the Optimized Multi-bit Trie (OMT) approach, maps a routing table having prefix entries and next hop identification (NHID) values into a compact and readily searchable data structure. LPM searches of the OMT data structure can be performed without backtracking and without loops on the trie level. LPM searches of the OMT data structure can be performed without performing condition checks. The OMT data structure is constructed for a routing table so that the LPM searches are performed according to a fixed number of levels. The OMT technique reduces the number of memory accesses required for identifying LPM matches and is fast and memory efficient.