Abstract: Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.

Abstract: A branch metric computation using limited bits by clipping the dynamic range and/or approximating the square of the difference between a sample value and the target value by a lookup table or piecewise linear with comparable slopes.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: Reduction of the complexity of a Viterbi-type sequence detector is disclosed. It was based on elimination of less probably taken branches in the trellis. The method is applied to the design of the E2PR4 channel with 8/9 rate sliding block trellis code. Coding, by itself eliminates two states by coding constraints, and the disclosed method reduces the number of required ACS units from 14 to 11, while reducing their complexity as well. For the implementation of E2PR4 detection, 4 4-way, 3 3-way, 3 2-way and one 1-way ACSs are needed. System simulations show no BER performance drop at common SNRs when compared with a full 16-state E2PR4 implementation in magnetic disk drives.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and Q. These signals have equal rising and falling transitions with the same delays for the Q signal and the Q signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: A method and system for encoding user data bits for magnetic recording channels that produces a stationary trellis and that limits the burst error propagation to three user bytes. The input data bits are grouped into even bytes and odd bytes. The even bytes are encoded first into even codewords, then each of the odd bytes is encoded into odd codewords based on the even codeword for the even byte preceding each odd byte and on the even codeword for the even byte following each odd byte. The encoding eliminates the most common error events associated with Partial Response Maximum Likelihood channels by: (i) disallowing sequences of four consecutive ones in the codewords, (ii) allowing sequences of three consecutive ones to begin only on certain bit positions in certain codewords, (iii) allowing only certain beginning sequences and ending sequences for odd and even codewords in specific situations, and (iv) changing specific bits in the odd and even codewords based on disallowed codeword sequences.