Patents by Inventor BORRONG HUANG

BORRONG HUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure for capacitor protection, package structure, and method of forming package structure
    Patent number: 11450732
    Abstract: A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 20, 2022
    Assignee: SUZHOU TF-AMD SEMICONDUCTOR CO. LTD.
    Inventors: Zhe Liu, Borrong Huang, Hongjie Wang, Diong Hing Ding
  • STRUCTURE FOR CAPACITOR PROTECTION, PACKAGE STRUCTURE, AND METHOD OF FORMING PACKAGE STRUCTURE
    Publication number: 20200286983
    Abstract: A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 10, 2020
    Inventors: Zhe LIU, BORRONG HUANG, HONGJIE WANG, DIONG HING DING