Abstract: In accordance with aspects of the present invention, embodiments of a photodiode circuit. A photodiode circuit according to some embodiments includes a transimpedance amplifier; a resistor coupled across the transimpedance amplifier; and an amplifier stage coupled to receive an output from the transimpedance amplifier, wherein the photodiode circuit provides dynamic range across a current range of the photodiode circuit. In some embodiments, the transimpedance amplifier includes a receive signal strength indicator that provides a DC current signal to a tail of a first amplifier stage, the tail providing a current that is adaptively related to the DC current. In some embodiments, the resistor is a shielded resistor. In some embodiments, the adaptive current sink includes a plurality of switchable parallel current sinks.

Abstract: In accordance with aspects of the present invention, embodiments of a photodiode circuit. A photodiode circuit according to some embodiments includes a transimpedance amplifier; a resistor coupled across the transimpedance amplifier; and an amplifier stage coupled to receive an output from the transimpedance amplifier, wherein the photodiode circuit provides dynamic range across a current range of the photodiode circuit. In some embodiments, the transimpedance amplifier includes a receive signal strength indicator that provides a DC current signal to a tail of a first amplifier stage, the tail providing a current that is adaptively related to the DC current. In some embodiments, the resistor is a shielded resistor. In some embodiments, the adaptive current sink includes a plurality of switchable parallel current sinks.

Abstract: Phase detectors for clock and data recovery circuits are provided herein. In certain implementations, a phase detector includes sampling circuitry that generates a plurality of samples of an input data signal based on timing of a plurality of clock signals, a binary response circuit that processes the plurality of samples to generate a plurality of binary output signals providing a binary detector response, and a linear response circuit that processes the plurality of samples to generate a plurality of linear output signals providing a linear detector response. The phase detector generates one or more data output signals based on the plurality of samples to thereby recover data from the input data signal.

Abstract: Phase detectors for clock and data recovery circuits are provided herein. In certain implementations, a phase detector includes sampling circuitry that generates a plurality of samples of an input data signal based on timing of a plurality of clock signals, a binary response circuit that processes the plurality of samples to generate a plurality of binary output signals providing a binary detector response, and a linear response circuit that processes the plurality of samples to generate a plurality of linear output signals providing a linear detector response. The phase detector generates one or more data output signals based on the plurality of samples to thereby recover data from the input data signal.