Abstract: A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.

Abstract: Semiconductor devices and a method for manufacturing the semiconductor devices are provided. The method includes forming a plurality of bit-line structures on a chip region of a substrate, forming a first alignment key pattern on a scribe line region of the substrate, forming a first alignment key trench in at least a portion of the first alignment key pattern, forming a landing pad layer between the plurality of bit-line structures and on top surfaces of the plurality of bit-line structures, forming a gap-fill layer on the landing pad layer and in an unoccupied portion of the first alignment key trench and performing a planarization process on the gap-fill layer and the landing pad layer.

Abstract: A semiconductor device including an upper insulating layer. In a cell area, the upper insulating layer may be in contact with a cell capping pattern, and in a core area the upper insulating layer is arranged to penetrate an insulating thin layer to be in contact with each of a core capping pattern, an insulating spacer, and an insulating thin layer.

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.