Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.