Abstract: An electrically erasable programmable read only memory (EEPROM) emulation (EEE) system includes a non-volatile memory arranged to have a plurality of sectors in which each sector is arranged to have a plurality of record locations. A new record of new data is programmed into a record location of an active sector of the plurality of sectors. After successfully completing the programming of the new record, a number of failure-to-program (FTP) occurrences during the programming is compared to a first threshold. When the number of FTP occurrences is greater than the first threshold, a determination is made as to whether compression is needed, and in response to determining that compression is needed, the method includes selectively performing compression based on a second threshold.

Abstract: An electrically erasable programmable read only memory (EEPROM) emulation (EEE) system includes a non-volatile memory arranged to have a plurality of sectors in which each sector is arranged to have a plurality of record locations. A new record of new data is programmed into a record location of an active sector of the plurality of sectors. After successfully completing the programming of the new record, a number of failure-to-program (FTP) occurrences during the programming is compared to a first threshold. When the number of FTP occurrences is greater than the first threshold, a determination is made as to whether compression is needed, and in response to determining that compression is needed, the method includes selectively performing compression based on a second threshold.

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: A non-volatile memory is arranged to have a plurality of sectors. Each sector of the plurality of sectors includes a plurality of record locations. A memory controller includes an erase counter, a failed sector flag, and a retired sector flag for each of the plurality of sectors. If a record location of a sector fails to program, another location in the sector is selected to be programmed. The failed sector flag is set if a predetermined number of selected record locations of the sector fails to program. If the failed sector flag is set for a particular sector twice, and an erase count is greater than a predetermined erase count, then the retired sector flag is set for the failed sector indicating the sector is to be permanently retired from use. A new sector of the plurality of sectors becomes the current active sector for record programming operations. The method for retiring a sector occurs dynamically, during operation of the non-volatile memory.

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).