Patents by Inventor BOTING LIU

BOTING LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12295162
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: May 6, 2025
    Assignee: HUNAN SAN'AN SEMICONDUCTOR CO., LTD.
    Inventors: Boting Liu, Yutao Fang, Shuai Chen, Nientze Yeh, Fuchin Chang
  • Publication number: 20240313088
    Abstract: An integrated semiconductor structure includes a silicon substrate, a silicon-based semiconductor device, and a nitride-based semiconductor device. The silicon substrate has a first area and a second area. The first area is formed with a trench that has a trench surface with a (111) orientation. The second area has an area surface with a (100) orientation. The silicon-based semiconductor device is disposed on the area surface with the (100) orientation. The nitride-based semiconductor device is disposed on the trench surface with the (111) orientation. A method for making the integrated semiconductor structure includes: a) providing a silicon substrate having first and second areas each having an area surface; b) forming a silicon-based semiconductor device on the area surface of the second area; c) wet etching the first area to form a trench having a trench surface; and d) forming a nitride-based semiconductor device on the trench surface.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Shenghou LIU, Wenbi CAI, Boting LIU, Xiguo SUN
  • Publication number: 20230104038
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 6, 2023
    Inventors: BOTING LIU, YUTAO FANG, SHUAI CHEN, NIENTZE YEH, FUCHIN CHANG
  • Patent number: 11508837
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: Xiamen Sanan Integrated Circuit Co., Ltd.
    Inventors: Yutao Fang, Boting Liu, Nien-Tze Yeh, Kaixuan Zhang
  • Publication number: 20200350426
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: YUTAO FANG, BOTING LIU, NIEN-TZE YEH, KAIXUAN ZHANG