Abstract: The nitride semiconductor device includes a first nitride layer including a binary nitride compound, a second nitride layer disposed on the first nitride layer and including a first element, a second element, and a third element, and a third nitride layer disposed on the second nitride layer and including the first element. A band gap of the third nitride layer is greater than that of the second nitride layer. A two-dimensional electron gas is generated in the first nitride layer. A maximum concentration value of the first element of the second nitride layer is no greater than a concentration value of the first element of the third nitride layer. Along a thickness direction, thicknesses the first nitride layer, the second nitride layer, and the third nitride layer is represented by d1, d2, and d3, respectively, where d2<d1, and 5 ??d2?60 ?.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: An integrated semiconductor structure includes a silicon substrate, a silicon-based semiconductor device, and a nitride-based semiconductor device. The silicon substrate has a first area and a second area. The first area is formed with a trench that has a trench surface with a (111) orientation. The second area has an area surface with a (100) orientation. The silicon-based semiconductor device is disposed on the area surface with the (100) orientation. The nitride-based semiconductor device is disposed on the trench surface with the (111) orientation. A method for making the integrated semiconductor structure includes: a) providing a silicon substrate having first and second areas each having an area surface; b) forming a silicon-based semiconductor device on the area surface of the second area; c) wet etching the first area to form a trench having a trench surface; and d) forming a nitride-based semiconductor device on the trench surface.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.

Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.