Patents by Inventor Botjo Atzema

Botjo Atzema has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of testing an analog-to-digital converter
    Patent number: 5854598
    Abstract: Only the value of the least-significant bit, or of some of the less-significant bits is used in order to test an analog-to-digital converter in an integrated circuit. The information concerning the differential and the integral non-linearity can be determined from the values of said less-significant bit. Furthermore, the functionality of the analog-to-digital converter is tested by counting the number of changes of the least-significant bit and by comparing this number with the value formed by the other bits.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: December 29, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Ronald De Vries, Botjo Atzema
  • Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing
    Patent number: 5781025
    Abstract: An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: July 14, 1998
    Assignee: U.S. Philips Corporation
    Inventors: Manoj Sachdev, Botjo Atzema
  • I.sub.DDQ -testing of bias generator circuit
    Patent number: 5751141
    Abstract: A bias generator is tested in an I.sub.DDQ -scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: May 12, 1998
    Assignee: U.S.Philips Corporation
    Inventors: Manoj Sachdev, Botjo Atzema