Patents by Inventor Bou Fun Chen

Bou Fun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5924001
    Abstract: A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by ion implantation is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. Silicon ions are implanted into the silicide layer. A hard mask layer is deposited over the silicide layer. Because of the presence of the silicon ions in the silicide layer, silicon atoms from the polysilicon layer do not diffuse into the silicide layer causing voids to form in the polysilicon layer. Therefore, the formation of silicon pits in the semiconductor substrate is prevented. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: July 13, 1999
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chie-Ming Yang, Jih-Wha Wang, Chien-Jiun Wang, Bou Fun Chen, Liang Szuma