Abstract: A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a circuit description. Then, the fan-out of each driving node is analyzed to determine if the total number of pass transistor loads of the analyzed node is excessive compared to a predetermined driving capacity. For each flagged node, logic equations are added which represent the sum of the node's pass transistor loads, and further logic equations are added to compare the number of pass transistors turned on from one to the absolute maximum for the node. Then, a formal proof program is used to analyze the logic circuit and determine which of the comparators have a true output.

Abstract: A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a circuit description. Then, the fan-out of each driving node is analyzed to determine if the total number of pass transistor loads of the analyzed node is excessive compared to a predetermined driving capacity. For each flagged node, logic equations are added which represent the sum of the node's pass transistor loads, and further logic equations are added to compare the number of pass transistors turned on from one to the absolute maximum for the node. Then, a formal proof program is used to analyze the logic circuit and determine which of the comparators have a true output.

Abstract: A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) when block writing the single value to the set of registers (60). Register address lines (110, 111) are decoded in two sets: a first set of decoded address lines (110) specifying a block of registers; and the second set (111) specifying one register in the block of registers. When the register block write signal (112) is asserted during a register write, the second set of decoded address lines (111) are ignored, and all registers in the block of registers (60) selected by the first set of decoded address lines (110) are simultaneously loaded with a common value. Additional drive requirements are solved either by adding a buffer (226) to each register bit, or by disabling (228) the feedback path (215) in each register bit during block writes.