Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: One example includes a clock distribution resonator system. The system includes a clock source configured to generate a clock signal having a predefined wavelength. The system also includes a plurality of transmission line branches each coupled to the clock source to propagate the clock signal. The system also includes a plurality of clock distribution networks coupled to the respective plurality of transmission line branches and being configured to provide the clock signal to each of a plurality of circuits. The system further includes at least one damping resonator. Each of the at least one damping resonator can be coupled to a respective at least one of the transmission line branches and configured to propagate the clock signal. The at least one damping resonator can have at least one resonator characteristic that is different relative to a respective resonator characteristic(s) associated with the transmission line branches and/or the clock distribution networks.

Abstract: Techniques for implementing tunable lumped element filters with transmission line sections. Transmission lines sections are used to implement one or more inductive or capacitance component elements of the filter. The filter is tunable by changing the dielectric constants of the transmission lines. In particular implementations there is an individual transmission line section for each lumped element component of a filter. Different filter circuits may be combined to provide a universal tunable filter assembly.

Abstract: A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Abstract: A variable capacitor structure using calibration plates, dual variable distance calibration plates, and/or interleaving extentions to the calibration plates.

Abstract: A tunable capacitor implemented as interdigitated arrays of finger elements arranged so that the spacing between finger arrays may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Abstract: Techniques for implementing tunable lumped element filters with transmission line sections. Transmission lines sections are used to implement one or more inductive or capacitance component elements of the filter. The filter is tunable by changing the dielectric constants of the transmission lines. In particular implementations there is an individual transmission line section for each lumped element component of a filter. Different filter circuits may be combined to provide a universal tunable filter assembly.

Abstract: A tunable capacitor implemented as interdigitated arrays of finger elements arranged so that the spacing between finger arrays may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Abstract: A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.