Abstract: The capacitively-coupled static random access memory (SRAM-C) compute-in-memory (CIM) circuit includes at least one static random access memory (SRAM) configured to store a bit value, at least one capacitively-coupled (CC) circuit coupled to at least one SRAM, and an energy recovery logic (ERL) driver configured to recover signal energy by utilizing a ramped sinusoidal hot clock. The CC circuit includes a first and second capacitors, a first pair, a second pair, a third pair, a fourth pair of transistors. Each pair of transistors include a first and second transistors coupled to one another. the first capacitor is coupled to the first and second pairs of transistors and the second capacitor is coupled to the third and fourth pairs of transistors. The SRAM-C CIM circuit enhances efficiency and effectiveness of multiply-and-accumulate (MAC) operations of the SRAM-C CIM circuit.

Abstract: A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converter (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that include PFETs and NFETs.

Abstract: A dynamic current rectifier includes an input terminal for receiving an input current, an output terminal for outputting a rectified output current, a first current mirror, a second current mirror, a first switch having a first terminal coupled to the input terminal and a second terminal coupled to the first current mirror, a second switch having a first terminal coupled to the output terminal and a second terminal coupled to the first current mirror, a third switch having a first terminal coupled to the input terminal and a second terminal coupled to the second current mirror, and a fourth switch having a first terminal coupled to the output terminal and a second terminal coupled to the second current mirror.

Abstract: The capacitively-coupled static random access memory (SRAM-C) compute-in-memory (CIM) circuit includes at least one static random access memory (SRAM) configured to store a bit value, at least one capacitively-coupled (CC) circuit coupled to at least one SRAM, and an energy recovery logic (ERL) driver configured to recover signal energy by utilizing a ramped sinusoidal hot clock. The CC circuit includes a first and second capacitors, a first pair, a second pair, a third pair, a fourth pair of transistors. Each pair of transistors include a first and second transistors coupled to one another. the first capacitor is coupled to the first and second pairs of transistors and the second capacitor is coupled to the third and fourth pairs of transistors. The SRAM-C CIM circuit enhances efficiency and effectiveness of multiply-and-accumulate (MAC) operations of the SRAM-C CIM circuit.

Abstract: A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converters (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that includes PFETs and NFETs.

Abstract: The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values.

Abstract: According to aspects of the present disclosure, a dynamic current mirror (DCM) is operated in a first stage and a second stage that is temporally subsequent to the first stage. The DCM includes a current memory cell and an inverting voltage amplifier. During the first stage, the current memory cell receives an input current and stores a corresponding voltage via a capacitance of the current memory cell. During the second stage, the current memory cell employs the stored input voltage to drive an output current that matches the input current. The inverting voltage amplifier is employed to increase the capacitance of the current memory cell via a Miller-effect amplification of the capacitance.

Abstract: A leakage compensation content addressable memory (CAM) circuit includes at least one CAM cell configured to store a bit value, and at least one compensation CAM cell configured to store the bit value of the CAM cell and to cancel leakage current of the CAM cell. The leakage compensation CAM circuit further includes at least one main bit line driver coupled to bit lines of the CAM cell to supply output to the bit lines of the CAM cell, at least one compensation bit line driver coupled to bit lines of the compensation CAM cell to supply output to the bit lines of the compensation CAM cell, and at least one word line driver coupled to word lines to supply output to the word lines of the CAM cell and the compensation CAM cell.

Abstract: A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converters (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that includes PFETs and NFETs.

Abstract: According to some other aspects of the present disclosure, an electrical circuit comprises a first capacitive element, a first transistor, a second capacitive element, and a second transistor. The circuit receives a first input current, a second input current, a third input current, and an input voltage. The circuit is configured to generate a first voltage by providing the input voltage and the first input current to the first transistor. The first voltage difference is the difference between the first voltage and the input voltage, and is logarithmically related to the first input current. The circuit may also be configured to store the first voltage as the first charged state of the first capacitive element. The circuit is further configured to generate a second voltage by providing the second input current and the first charged state of the first capacitive element to the first transistor.

Abstract: According to some other aspects of the present disclosure, an electrical circuit comprises a first capacitive element, a first transistor, a second capacitive element, and a second transistor. The circuit receives a first input current, a second input current, a third input current, and an input voltage. The circuit is configured to generate a first voltage by providing the input voltage and the first input current to the first transistor. The first voltage difference is the difference between the first voltage and the input voltage, and is logarithmically related to the first input current. The circuit may also be configured to store the first voltage as the first charged state of the first capacitive element. The circuit is further configured to generate a second voltage by providing the second input current and the first charged state of the first capacitive element to the first transistor.

Abstract: The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values.

Abstract: Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Abstract: A dynamic current rectifier includes an input terminal for receiving an input current, an output terminal for outputting a rectified output current, a first current mirror, a second current mirror, a first switch having a first terminal coupled to the input terminal and a second terminal coupled to the first current mirror, a second switch having a first terminal coupled to the output terminal and a second terminal coupled to the first current mirror, a third switch having a first terminal coupled to the input terminal and a second terminal coupled to the second current mirror, and a fourth switch having a first terminal coupled to the output terminal and a second terminal coupled to the second current mirror.

Abstract: Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Abstract: Phase detectors are provided. In one example, The phase detector may include a first transistor leg and a second transistor leg. Each of the first transistor leg and the second transistor leg may include a pair of transistors coupled together at a plurality of common nodes. The phase detector may include an input at the first transistor leg. The input may be configured to receive a first input signal and a second input signal. The phase detect may include an output coupled to the second transistor leg. The output may be configured to provide an output signal. The output signal may include a component indicative of a phase difference between the first input signal and the second input signal.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.

Abstract: Trap circuits for use with superconducting integrated circuits having differential capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a first superconducting circuit comprising: (1) a first Josephson junction (JJ) coupled via a first capacitor to a first clock line, where the first capacitor is configured to receive a first clock signal having a first phase via the first clock line and couple a first bias current to the first JJ, and (2) a second JJ coupled via a second capacitor to a second clock line, where the second capacitor is configured to receive a second clock signal having a second phase via the second clock line and couple a second bias current to the second JJ. The superconducting IC further includes a first trap circuit for the first superconducting circuit and a second trap circuit for a second superconducting circuit having additional JJs.

Abstract: Trap circuits for use with superconducting integrated circuits having capacitively-coupled resonant clock networks are described. An example superconducting integrated circuit (IC) includes a clock structure coupled: (1) to a first Josephson junction (JJ) via a first capacitor, where the first capacitor is configured to receive a clock signal via the clock structure and couple a first bias current to the first JJ, and (2) to a second JJ via a second capacitor, where the second capacitor is configured to receive a clock signal via the clock structure and couple a second bias current to the second JJ. The superconducting IC further includes a trap circuit coupled between the first capacitor and the first JJ, where the trap circuit is configured to attenuate any signals generated by a triggering of the first JJ to reduce crosstalk between the first JJ and the second JJ.