Patents by Inventor Boxiao LIU

Boxiao LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electrical impedance tomography with FDM-based data compression
    Patent number: 11730386
    Abstract: An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 22, 2023
    Assignees: Shanghai Jiao Tong University, National University of Singapore
    Inventors: Boxiao Liu, Yong Lian, Lei Zeng, Chun Huat Heng
  • ELECTRICAL IMPEDANCE TOMOGRAPHY WITH FDM-BASED DATA COMPRESSION
    Publication number: 20200146585
    Abstract: An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 14, 2020
    Inventors: Boxiao LIU, Yong Lian, Lei Zeng, Chun Huat Heng