Abstract: A method and apparatus are provided for aligning and laminating stiffeners to substrates in electrical circuits. Generally, this method includes placing a substrate within an alignment frame or tool; applying an adhesive on the substrate; placing a stiffener on the adhesive to form a chip package; applying sufficient pressure and heat to the package for a sufficient time to cure the adhesive. Another method of the present invention includes placing a substrate within an alignment tool or frame; applying an adhesive on the substrate within the alignment tool; placing a stiffener on the adhesive to form a package; applying sufficient heat and pressure to the package for a sufficient time to tack the stiffener to the substrate; removing the package from the alignment tool or frame; and heating the package for a sufficient time and temperature to cure the adhesive wherein the stiffener enhances rigidity of the package.

Abstract: A method and apparatus are provided for coining solder balls on an organic electrical circuit package. Generally, this method includes placing a slug on one or more of the solder balls; and applying sufficient pressure for a sufficient period of time on the slug to flatten the surface of the solder balls so as to form planar solder coins. The apparatus includes a press; a ram attached to the press; a platform for receiving the package and a slug placed upon the solder balls.

Abstract: A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer.