Patents by Inventor Boyin Chen

Boyin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153809
    Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: November 26, 2024
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Yueer Shan, Yanfeng Xu, Boyin Chen, Zhan Jing
  • Patent number: 12099377
    Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: September 24, 2024
    Assignee: WUXI ESIONTECH CO., LTD.
    Inventors: Chenguang Kuang, Yanfei Zhang, Boyin Chen, Jicong Fan
  • Publication number: 20230385222
    Abstract: A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: WUXI ESIONTECH CO., LTD.
    Inventors: Xiaojie MA, Yanfeng XU, Yuting XU, Boyin CHEN, Yanfei ZHANG, Yueer SHAN
  • Publication number: 20230016311
    Abstract: A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Applicant: WUXI ESIONTECH CO., LTD.
    Inventors: Chenguang KUANG, Yanfei ZHANG, Boyin CHEN, Jicong FAN
  • Publication number: 20220113883
    Abstract: A field-programmable gate array (FPGA) for implementing data transfer between different configuration and application processes includes a programmable logic resource, a configuration memory and a hardware memory. A write port and a read port of the hardware memory are respectively connected to a programmable logic resource by a wiring path, data in the hardware memory remains unchanged at an abnormal running stage of the programmable logic resource, and running data generated by a user design in a configuration and application process can be transferred to a user design in a subsequent configuration and application process by using the hardware memory for use during running. This enlarges functions of the FPGA, and meets application requirements in a plurality of different scenarios.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Applicant: WUXI ESIONTECH CO., LTD.
    Inventors: Yueer Shan, Yanfeng Xu, Boyin Chen, Zhan Jing