Patents by Inventor Brad Besmer

Brad Besmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9531807
    Abstract: Methods and systems for configuring network storage are presented. A method for configuring network storage may include: detecting one more connection rates associated with one or more input PHYs associated with one or more parent devices; detecting a number of input connections associated with one or more PHYs associated with one or more parent devices; setting one or more connection rates associated with one or more input PHYs associated with one or more child devices according to the one or more connection rates associated with the one or more input PHYs associated with the one or more parent devices; and setting a number of input connections associated with one or more PHYs associated with one or more child devices according to a number of input connections associated with one or more PHYs associated with one or more parent devices.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: December 27, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Owen N. Parry, Minjen Wang, Brad Besmer
  • Patent number: 8843666
    Abstract: A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: September 23, 2014
    Assignee: LSI Corporation
    Inventors: Brad Besmer, Brian A. Day, Scott Dominguez, Kevin A. Mocklin, David J. Golden
  • Publication number: 20130232281
    Abstract: A SAS expander or initiator places PHYs in a wide port into a persistent reduced power state by signaling to the connected SAS device that the SAS expander or initiator intends to route data traffic through other PHYs in the wide port. The SAS expander or initiator and connected SAS device agree to disuse certain PHYs so that the PHYs enter a reduced power state according to SAS standards.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Applicant: LSI CORPORATION
    Inventors: Brad Besmer, Brian Day, Scott Dominguez, Kevin Mocklin, David Golden
  • Publication number: 20110246677
    Abstract: Methods and systems use a hardware controller for controlling commands sent to a plurality of target devices. The controller controls queuing of commands according to respective target device allowed queue depths set in hardware circuitry of the controller. Status of each one of the plurality of target devices is monitored also using controller hardware circuitry. The allowed queue depths can be set in the hardware controller circuitry using firmware and can by dynamically adjustable based on the status of the target devices. Hardware circuitry of the controller is also used to control queuing of commands, for each one of the plurality of target devices, according to the queue depth setting for the target device.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 6, 2011
    Inventors: Stephen Johnson, Timothy Hoglund, Larry Rawe, Nick Pelis, Brad Besmer
  • Publication number: 20100281172
    Abstract: Methods and systems for configuring network storage are presented. A method for configuring network storage may include: detecting one more connection rates associated with one or more input PHYs associated with one or more parent devices; detecting a number of input connections associated with one or more PHYs associated with one or more parent devices; setting one or more connection rates associated with one or more input PHYs associated with one or more child devices according to the one or more connection rates associated with the one or more input PHYs associated with the one or more parent devices; and setting a number of input connections associated with one or more PHYs associated with one or more child devices according to a number of input connections associated with one or more PHYs associated with one or more parent devices.
    Type: Application
    Filed: April 30, 2009
    Publication date: November 4, 2010
    Inventors: Owen N. Parry, Minjen Wang, Brad Besmer
  • Publication number: 20060253684
    Abstract: A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.
    Type: Application
    Filed: May 9, 2005
    Publication date: November 9, 2006
    Inventors: Stephen Johnson, Brad Besmer, Timothy Hoglund, Jana Richards
  • Publication number: 20060101085
    Abstract: The present invention is directed to a method and system for efficient write journal entry management maintaining minimum write journal information stored in a nonvolatile memory through utilizing an additional structure in a fast volatile memory. The method and system may manage write journaling of a file volume including multiple fixed sized regions and assign a persistent 1-bit synchronization status (the write journal information) to each data region. In addition, a non-persistent I/O counter (the additional structure) for each region to manage the persistent 1-bit synchronization status during run-time. The present invention may provide a mechanism to determine when write I/O operations have not successfully completed to a specific region of the file volume.
    Type: Application
    Filed: October 26, 2004
    Publication date: May 11, 2006
    Inventors: Paul Soulier, Brad Besmer
  • Patent number: 6934803
    Abstract: Methods and associated structure for mapping of data stripes and stripes in a RAID level 1E storage subsystem such that associated stripes of multiple physical stripes are physically contiguous. This mapping eliminates the need for duplicative reading (or writing) of stripes unrelated to the underlying I/O request performed to reduce the total number of I/O requests. This mapping also serves to limit the number of I/O requests required to read multiple stripes to the number of disk drives in the array and the number required to write multiple stripes and their corresponding mirrors to twice the number of disk drives in the array. The effects of this mapping therefore simplify RAID level 1E management in RAID controller with constrained memory and processing resources.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: August 23, 2005
    Assignee: LSI Logic Corporation
    Inventors: Paul Soulier, Brad Besmer
  • Publication number: 20030225794
    Abstract: Methods and associated structure for mapping of data stripes and stripes in a RAID level 1E storage subsystem such that associated stripes of multiple physical stripes are physically contiguous. This mapping eliminates the need for duplicative reading (or writing) of stripes unrelated to the underlying I/O request performed to reduce the total number of I/O requests. This mapping also serves to limit the number of I/O requests required to read multiple stripes to the number of disk drives in the array and the number required to write multiple stripes and their corresponding mirrors to twice the number of disk drives in the array. The effects of this mapping therefore simplify RAID level 1E management in RAID controller with constrained memory and processing resources.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Paul Soulier, Brad Besmer