Patents by Inventor Brad D. Besmer

Brad D. Besmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9767117
    Abstract: The present invention is directed to a method and system for efficient write journal entry management maintaining minimum write journal information stored in a nonvolatile memory through utilizing an additional structure in a fast volatile memory. The method and system may manage write journaling of a file volume including multiple fixed sized regions and assign a persistent 1-bit synchronization status (the write journal information) to each data region. In addition, a non-persistent I/O counter (the additional structure) for each region to manage the persistent 1-bit synchronization status during run-time. The present invention may provide a mechanism to determine when write I/O operations have not successfully completed to a specific region of the file volume.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 19, 2017
    Assignee: NetApp, Inc.
    Inventors: Paul E. Soulier, Brad D. Besmer
  • Patent number: 9298648
    Abstract: Disclosed is a system and method for generating IO in PCIe devices and flow management of the IO.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: March 29, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Stephen B. Johnson, Brad D. Besmer, Lawrence J. Rawe, Gerald E. Smith
  • Patent number: 9213588
    Abstract: A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 15, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Naman Nair, Brad D. Besmer, Peter C. Rivera, James Rizzo
  • Publication number: 20150199227
    Abstract: A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period, a reporting initiator reports a detection of a faulty link in the multi-initiator topology and requests an arbitrator to identify at least one peer initiator in the multi-initiator topology that shares at least one shared link with the reporting initiator. This reporting initiator and its peer initiators then jointly execute a common diagnostic process to identify the faulty link in the multi-initiator topology.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 16, 2015
    Applicant: LSI Corporation
    Inventors: Naman Nair, Brad D. Besmer, Peter C. Rivera, James Rizzo
  • Patent number: 9021199
    Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: April 28, 2015
    Assignee: LSI Corporation
    Inventors: Nilesh S. Govande, Jameer Babasaheb Mulani, Brad D. Besmer, Susan Gray
  • Patent number: 8996748
    Abstract: A storage system and method for preventing propagation of link reset among initiators in the storage system is disclosed. The method includes issuing a link reset command by the initiator, and entering the initiator into a back-off period immediately following the issuing of the link reset command. The initiator remains idle for the entire duration of the back-off period and resumes its operations at the end of the back-off period.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: March 31, 2015
    Assignee: LSI Corporation
    Inventors: Naman Nair, Brad D. Besmer, Peter C. Rivera, James Rizzo
  • Patent number: 8904158
    Abstract: The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and Ethernet connection which may be used for providing alerts regarding the health of the components of the boot appliance and/or data storage system to a monitoring system, such as a network management system. The boot appliance may provide a boot drive and operating system image to multiple servers at the same time.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: December 2, 2014
    Assignee: LSI Corporation
    Inventors: Gregory L. Huff, Timothy E. Hoglund, Brad D. Besmer, Mark J. Jander, Edward F. Marchand, Jason C. McGinley
  • Publication number: 20140337540
    Abstract: Disclosed is a system and method for generating IO in PCIe devices and flow management of the IO.
    Type: Application
    Filed: December 4, 2013
    Publication date: November 13, 2014
    Applicant: LSI CORPORATION
    Inventors: Stephen B. Johnson, Brad D. Besmer, Lawrence J. Rawe, Gerald E. Smith
  • Publication number: 20140245300
    Abstract: A system to allow reallocation of credit among virtual machines associated with separate operating systems includes drivers in each virtual machine to independently track credit usage and a host board adapter configured to report a false maximum to each operating system and track credit usage. The host board adapter allocates credits and reports the allocated credits to virtual functions accessed by the virtual machines. A hypervisor reallocates credits by reporting the new allocation to the host board adapter and consequently to each virtual function and each associated virtual machine. Each operating system maintains resources defined by the false maximum and never knows about the reallocation.
    Type: Application
    Filed: March 1, 2013
    Publication date: August 28, 2014
    Applicant: LSI Corporation
    Inventors: Roger T. Clegg, Peter C. Rivera, Brad D. Besmer, Steven R. Schremmer
  • Patent number: 8677095
    Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 18, 2014
    Assignee: LSI Corporation
    Inventors: Roger T. J Clegg, Brad D. Besmer, Guy Kendall
  • Publication number: 20140052908
    Abstract: Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance zones exhibit different performance criteria for one or more of: reading data from the storage device and writing data to the storage device. The storage controller is further adapted to allocate storage from each of the plurality of performance zones for each of the plurality of logical volumes such that the performance criteria for accessing the storage device is distributed substantially uniformly across the plurality of logical volumes.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: LSI CORPORATION
    Inventors: Nilesh S. Govande, Jameer Babasaheb Mulani, Brad D. Besmer, Susan Gray
  • Publication number: 20130268492
    Abstract: The present invention is directed to a method and system for efficient write journal entry management maintaining minimum write journal information stored in a nonvolatile memory through utilizing an additional structure in a fast volatile memory. The method and system may manage write journaling of a file volume including multiple fixed sized regions and assign a persistent 1-bit synchronization status (the write journal information) to each data region. In addition, a non-persistent I/O counter (the additional structure) for each region to manage the persistent 1-bit synchronization status during run-time. The present invention may provide a mechanism to determine when write I/O operations have not successfully completed to a specific region of the file volume.
    Type: Application
    Filed: May 16, 2013
    Publication date: October 10, 2013
    Applicant: NetApp, Inc.
    Inventors: Paul E. Soulier, Brad D. Besmer
  • Patent number: 8458238
    Abstract: The present invention is directed to a method and system for efficient write journal entry management maintaining minimum write journal information stored in a nonvolatile memory through utilizing an additional structure in a fast volatile memory. The method and system may manage write journaling of a file volume including multiple fixed sized regions and assign a persistent 1-bit synchronization status (the write journal information) to each data region. In addition, a non-persistent I/O counter (the additional structure) for each region to manage the persistent 1-bit synchronization status during run-time. The present invention may provide a mechanism to determine when write I/O operations have not successfully completed to a specific region of the file volume.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: June 4, 2013
    Assignee: NETAPP, Inc.
    Inventors: Paul E. Soulier, Brad D. Besmer
  • Publication number: 20130061029
    Abstract: The present invention is directed to a boot appliance for a data storage system. The boot appliance is a self-contained, pre-configured device that serves as a boot device for multiple servers. The boot appliance contains multiple hard drives which are configured into one or more RAID volumes. Each volume is divided into multiple partitions, with each partition serving as the boot drive for any server connected to it. The boot appliance provides its own environmental controls and Ethernet connection which may be used for providing alerts regarding the health of the components of the boot appliance and/or data storage system to a monitoring system, such as a network management system. The boot appliance may provide a boot drive and operating system image to multiple servers at the same time.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 7, 2013
    Applicant: LSI CORPORATION
    Inventors: Gregory L. Huff, Timothy E. Hoglund, Brad D. Besmer, Mark J. Jander, Edward F. Marchand, Jason C. McGinley
  • Patent number: 8239701
    Abstract: Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: August 7, 2012
    Assignee: LSI Corporation
    Inventors: Brian A. Day, Brad D. Besmer
  • Patent number: 8219719
    Abstract: An apparatus and method are disclosed for maintaining consistent port and PHY configuration information in an SAS controller when connected SAS devices are rebooted, reset or otherwise temporarily disconnected. Configuration information is stored in non-volatile memory, and restored by a methodology to prevent port conflicts.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 10, 2012
    Assignee: LSI Corporation
    Inventors: Owen Parry, Brad D. Besmer, Ming-Jen Wang
  • Publication number: 20110029787
    Abstract: Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more voltage levels provided by the power supply. In other exemplary embodiments, the messages may designate the duration of time during which the requesting device may utilize the allocated power. A power status message from the device to the controller may indicate a change in the power consumption by the device. Responsive to the power status message the controller may re-allocate power previously allocated to a device that has completed use thereof.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 3, 2011
    Applicant: LSI CORPORATION
    Inventors: Brian A. Day, Brad D. Besmer
  • Publication number: 20100131734
    Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Inventors: Roger T. J. Clegg, Brad D. Besmer, Guy Kendall
  • Patent number: 7617428
    Abstract: Circuits and associated methods for testing internal operation of an application integrated circuit. Features and aspects hereof add configurable test interrupt circuits to an application circuit design to permit dynamic, configurable interrupt generation from an integrated circuit based on conditions determined from monitoring of internal signals of the application circuit. The internal signals that may be tested and used to generate test interrupts are those not exposed to the external processor interface of the integrated circuit and thus may be configured to interrupt based on any internal state of the application specific functional circuits of the integrated circuit.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: November 10, 2009
    Assignee: LSI Corporation
    Inventors: Paul J. Smith, Brad D. Besmer, Guy W. Kendall
  • Patent number: 7590819
    Abstract: A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integrated circuit device remains small notwithstanding such enhanced functionality. This compact/tiny MMU provides virtual memory addressing and memory error detection functionality while maintaining a small physical die size. The small physical die size with enhanced functionality is obtained by improvements in translating virtual to physical addressing without use of extensive translation tables, which themselves would otherwise consume memory and associated die real estate. In addition, the MMU allows a firmware image containing code and data segments to be run-time swapped between internal shared context RAM and external memory.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: September 15, 2009
    Assignee: LSI Logic Corporation
    Inventors: Stephen B. Johnson, Brad D. Besmer, Timothy E. Hoglund, Jana L. Richards