Abstract: A signal generator includes a data source, a power source, and a modulator. The modulator is configured to modulate a power signal from the power source with a data signal from the data source to generate a modulated power signal. Data values of the data signal correspond to variations in a voltage level of the modulated power signal over time. The modulator is coupled to output the modulated data signal to a one-wire interface.

Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.

Abstract: Embodiments of a linear voltage regulator are described. In one embodiment, the linear voltage regulator includes a PMOS low drop-out (LDO) regulator configured to convert an input voltage to a regulated voltage, a charge pump connected to the PMOS LDO regulator and configured to amplify the regulated voltage into an amplified voltage, and an NMOS LDO regulator connected to the charge pump and configured to convert the amplified voltage into an output voltage. Other embodiments are also described.

Abstract: A reference output device includes a low side selector configured to select a first voltage level as an output signal. The output signal is a reference voltage. The reference output device also includes a high side selector configured to select a second voltage level as the output signal. The reference output device also includes a slew rate control configured to switch the output signal between the first voltage level and the second voltage level at a constant slew rate.

Abstract: Embodiments of a linear voltage regulator are described. In one embodiment, the linear voltage regulator includes a PMOS low drop-out (LDO) regulator configured to convert an input voltage to a regulated voltage, a charge pump connected to the PMOS LDO regulator and configured to amplify the regulated voltage into an amplified voltage, and an NMOS LDO regulator connected to the charge pump and configured to convert the amplified voltage into an output voltage. Other embodiments are also described.

Abstract: A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).