Patents by Inventor Brad Herner

Brad Herner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139998
    Abstract: Devices and methods of their fabrication for pixels or displays are disclosed. Pixels and displays having redundant subpixels are described. Subpixels are initially isolated by an unprogrammed antifuse. A subpixel is connected to the display by programming the antifuse, electrically connecting it to the pixel or display. Defective subpixels can be determined by photoluminescent testing or electroluminescent testing, or both. A redundant subpixel can replace a defective subpixel before pixel or display fabrication is complete.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 5, 2022
    Applicant: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11309331
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 19, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 11282855
    Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 22, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Wu-Yi Henry Chien, Jie Zhou, Eli Harari
  • Publication number: 20220077189
    Abstract: A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Inventors: Scott Brad Herner, Eli Harari
  • Publication number: 20220068951
    Abstract: A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 3, 2022
    Inventors: Scott Brad Herner, Eli Harari
  • Publication number: 20220037356
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Publication number: 20220028920
    Abstract: This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 27, 2022
    Applicant: Black Peak LLC
    Inventor: Scott Brad Herner
  • Publication number: 20220028871
    Abstract: A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, N2O, and NH3 gas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Scott Brad Herner, Christopher J. Petti, George Samachisa, Wu-Yi Henry Chien
  • Publication number: 20210407983
    Abstract: A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of a interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Scott Brad Herner, Eli Harari
  • Patent number: 11211398
    Abstract: A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: December 28, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Publication number: 20210398949
    Abstract: An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die.
    Type: Application
    Filed: September 3, 2021
    Publication date: December 23, 2021
    Inventors: Khandker Nazrul Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner, Siu Lung Chan, Sayeef Salahuddin, Mehrdad Mofidi, Eli Harari
  • Publication number: 20210384382
    Abstract: This application describes a light emitting device or an assembly of light emitting devices. In the completed light emitting device, a distributed Bragg reflector minimizes the possibility of disturbing adjacent light emitting devices. Methods to fabricate such devices and assemblies of devices are also described.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Applicant: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11183534
    Abstract: This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 23, 2021
    Assignee: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11177281
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 16, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Chien
  • Patent number: 11158620
    Abstract: A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of an interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: October 26, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Eli Harari
  • Publication number: 20210320182
    Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 14, 2021
    Inventors: Wu-Yi Henry Chien, Scott Brad Herner, Eli Harari
  • Publication number: 20210313348
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Application
    Filed: June 15, 2021
    Publication date: October 7, 2021
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Publication number: 20210305464
    Abstract: This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Applicant: Black Peak LLC
    Inventor: Scott Brad Herner
  • Patent number: 11133439
    Abstract: This application describes a light emitting device or an assembly of light emitting devices. In the completed light emitting device, a distributed Bragg reflector minimizes the possibility of disturbing adjacent light emitting devices. Methods to fabricate such devices and assemblies of devices are also described.
    Type: Grant
    Filed: May 3, 2020
    Date of Patent: September 28, 2021
    Assignee: Black Peak LLC
    Inventor: Scott Brad Herner
  • Publication number: 20210225873
    Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Applicant: SUNRISE MEMORY CORPORATION
    Inventor: Scott Brad Herner