Abstract: A processor system is disclosed that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. ECC hardware circuitry provides detection, correction and generation of ECC data bits in conjunction with memory data read and writes. The disclosed methodology permits the detection and correction of soft single bit errors read from local memory in-line while using read modify write DMA circuit logic to correct local memory data. The disclosed methodology provides local memory data error detection and correction in a background memory scrub process without the need for additional in-line data logic.

Abstract: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

Abstract: A preferred embodiment of the present invention provides a method, computer program product, and processor design for supporting high-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, a preferred embodiment of the present invention incurs significantly less overhead than would specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

Abstract: An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the pipeline. A state machine detects incorrect results within the pipeline and sends the incorrect results to the replay loop. A correction module on the replay loop repairs the incorrect results and transmits the repaired results back into the pipeline. When an incorrect result enters the replay loop, a flush operation: ceases other operations within the pipeline; flushes the rest of the data results in the pipeline to the replay loop; opens the pipeline for the repaired results to be inserted; and eliminates any operations within the processor that would utilize the incorrect results.

Abstract: A system and method that maintains a relatively small Instruction Load Buffer (ILB) is maintained for scheduling instructions. Instructions are sent from Local Store (LS) to the ILB using either an inline prefetcher or a branch table buffer loader. In one embodiment, the prefetcher is a hardware-based prefetcher that fetches, in address order, the next instructions likely to be scheduled. In one embodiment, the predicted branch instructions are loaded as a result of a software program, such as a dispatcher, issuing a “load branch table buffer (loadbtb)” instruction. Predicted branch instructions are loaded in one area of the ILB and inline instructions are loaded in another area of the ILB. In one embodiment, the loadbtb loads the instruction line that includes the predicted branch target address as well as the instruction line that immediately follows the instruction line with the predicted branch target address.

Abstract: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.