Abstract: A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt endpoint. The method further includes initializing the primary and secondary interrupt queue heads. The method also includes scheduling the primary and secondary queue heads in immediately subsequent frames.

Abstract: A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

Abstract: A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

Abstract: A timing enhancement for a USB controller determines if a short data packet is present. If so, data is placed in a buffer. If the buffer is full, data is sent. If the buffer is not full, the system looks to see if more data is available, if so takes it, if not it sends whatever is available.

Abstract: A method for identifying a logic event in a logic environment, the method including providing one of a reference parameter and a next reference parameter, receiving starting event information corresponding to a logic event, ending event information corresponding to the logic event, and at least one identification parameter information associated with the logic event, determining an actual parameter corresponding to at least one of a duration parameter and a capacity parameter corresponding to the logic event, comparing the actual parameter to the reference parameter and providing a comparison result, and if the comparison result at least indicates that the actual parameter is no less than the reference parameter, performing at least one of replacing the reference parameter with the actual parameter to provide the next reference parameter and providing the at least one identification parameter.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt endpoint. The method further includes initializing the primary and secondary interrupt queue heads. The method also includes scheduling the primary and secondary queue heads in immediately subsequent frames.

Abstract: Apparatus and methods to control an external bus. In one embodiment, an apparatus includes an external bus port and an external bus controller. The external bus controller can include a first register interface to receive a first set of data and a second register interface to receive a second set of data. The external bus controller can send the first set of data and the second set of data to said external bus port.

Abstract: A method and apparatus for ensuring frame integrity in a bus system are disclosed. In the disclosed system, each scheduled transaction is evaluated before execution to determine whether there is enough time in the frame to complete the transaction. By separately evaluating each transaction at the time of execution, held off transactions are not aborted if the frame ends before the transaction completes. Each transaction is evaluated by determining the approximate length of the transaction and comparing the approximate length to the number of byte times remaining in the frame. A step function is used to determine the approximate length by adding one of two possible constant values which take into account transaction overhead to the number of data bytes in the transaction, the selected constant value being dependent upon the number of data bytes, a smaller constant value being added for smaller transactions and a larger transaction value being added for larger transactions.

Abstract: Security from an unwanted intrusion into a computer system is provided by coupling a host component with a peripheral component using a high-speed serial bus having a high-speed physical layer and using features of the bus to implement the security. In an embodiment, the high-speed serial bus has a secondary bus layer that is used to implement a number of the security features of the invention.

Abstract: An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers.

Abstract: A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.