Patents by Inventor Brad William Michael
Brad William Michael has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230060194Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Eric E. Retter, Lilith Hale, Brad William Michael, John Dodson
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Patent number: 11372703Abstract: A memory controller receives, via a first interface, a first read request requesting a requested data granule. Based on receipt of the first read request, the memory controller transmits, via a second interface, a second read request to initiate access of the requested data granule from a system memory. Based on a determination to schedule accelerated data delivery and receipt by the memory controller of a data scheduling indication that indicates a timing of future delivery of the requested data granule, the memory controller requests, prior to receipt of the requested data granule, permission to transmit the requested data granule on the system interconnect fabric. Based on receipt of the requested data granule at the indicated timing and a grant of the permission to transmit, the memory controller initiates transmission of the requested data granule on the system interconnect fabric and transmits an error indication for the requested data granule.Type: GrantFiled: February 19, 2021Date of Patent: June 28, 2022Assignee: International Business Machines CorporationInventors: John Samuel Liberty, Brad William Michael, Stephen J. Powell, Nicholas Steven Rolfe
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Patent number: 8677101Abstract: A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code.Type: GrantFiled: June 7, 2007Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Brian Flachs, Harm Peter Hofstee, Brad William Michael
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Patent number: 8516230Abstract: An application thread executes a direct branch instruction that is stored in an instruction cache line. Upon execution, the direct branch instruction branches to a branch descriptor that is also stored in the instruction cache line. The branch descriptor includes a trampoline branch instruction and a target instruction space address. Next, the trampoline branch instruction sends a branch descriptor pointer, which points to the branch descriptor, to an instruction cache manager. The instruction cache manager extracts the target instruction space address from the branch descriptor, and executes a target instruction corresponding to the target instruction space address. In one embodiment, the instruction cache manager generates a target local store address by masking off a portion of bits included in the target instruction space address. In turn, the application thread executes the target instruction located at the target local store address accordingly.Type: GrantFiled: December 29, 2009Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Tong Chen, Brian Flachs, Brad William Michael, Mark Richard Nutter, Kathryn M. O'Brien, John Kevin Patrick O'Brien
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Patent number: 8145804Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: GrantFiled: September 21, 2009Date of Patent: March 27, 2012Assignees: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Patent number: 7986330Abstract: A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.Type: GrantFiled: April 12, 2001Date of Patent: July 26, 2011Assignee: International Business Machines CorporationInventors: Daniel Alan Brokenshire, Bruce David D'Amora, Gordon Clyde Fossum, Charles Ray Johns, John Samuel Liberty, Brad William Michael
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Publication number: 20110161641Abstract: An application thread executes a direct branch instruction that is stored in an instruction cache line. Upon execution, the direct branch instruction branches to a branch descriptor that is also stored in the instruction cache line. The branch descriptor includes a trampoline branch instruction and a target instruction space address. Next, the trampoline branch instruction sends a branch descriptor pointer, which points to the branch descriptor, to an instruction cache manager. The instruction cache manager extracts the target instruction space address from the branch descriptor, and executes a target instruction corresponding to the target instruction space address. In one embodiment, the instruction cache manager generates a target local store address by masking off a portion of bits included in the target instruction space address. In turn, the application thread executes the target instruction located at the target local store address accordingly.Type: ApplicationFiled: December 29, 2009Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: TONG CHEN, BRIAN FLACHS, BRAD WILLIAM MICHAEL, MARK RICHARD NUTTER, KATHRYN M. O'BRIEN, JOHN KEVIN PATRICK O'BRIEN
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Publication number: 20110072170Abstract: A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.Type: ApplicationFiled: September 21, 2009Publication date: March 24, 2011Inventors: Brian King Flachs, Brad William Michael, Nicolas Maeding, Shigeaki Iwasa, Seiji Maeda, Hiroo Hayashi
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Publication number: 20080307201Abstract: A processor system executes multiple applet programs within a software application program in an information handling system. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In particular, the operating system software manages partitioning of a register file in the processor system to achieve a cooperative relationship among multiple applet programs within respective partitions of the register file. In one embodiment, the operating system software manages unique applet ID's to modify register file partition sizes and locations during applet program instruction text execution. In one embodiment, applet ID masking hardware provides sharing of register file space among multiple copies of applet program code.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Applicant: IBM CorporationInventors: Brian Flachs, Harm Peter Hofstee, Brad William Michael
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Publication number: 20080263336Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: ApplicationFiled: June 24, 2008Publication date: October 23, 2008Applicant: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7406589Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.Type: GrantFiled: May 12, 2005Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad William Michael, Silvia Melitta Mueller, Hwa-Joon Oh
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Patent number: 7203608Abstract: A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement.Type: GrantFiled: June 16, 2006Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Makoto Aikawa, Sang Hoo Dhong, Brian Flachs, Paul Marlan Harvey, Brad William Michael, Yaping Zhou
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Patent number: 7149877Abstract: A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.Type: GrantFiled: July 17, 2003Date of Patent: December 12, 2006Assignee: International Business Machines CorporationInventors: Sang Hoo Dhong, Hwa-Joon Oh, Brad William Michael, Silvia Melitta Mueller, Kevin D. Tran
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Publication number: 20020158885Abstract: A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.Type: ApplicationFiled: April 12, 2001Publication date: October 31, 2002Inventors: Daniel Alan Brokenshire, Bruce David D'Amora, Gordon Clyde Fossum, Charles Ray Johns, John Samuel Liberty, Brad William Michael
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Patent number: 6421053Abstract: Primitives are divided into span groups of 2N spans, and then processed in M×N blocks of pixels, with the pixel blocks preferably being as close to square as possible and therefore optimized for small spans and texture mapping. Each span group is rendered block-by-block in a serpentine manner from an initial or entry block, first in a direction away from the long edge of the primitive and then in a direction towards the long edge. The interpolators include a one-deep stack onto which pixel and texel information for the initial or entry block are pushed before rendering any other blocks within the span group. Blocks or pairs of blocks within different span subgroups of the span group are then alternately rendered, such that rendering zig-zags between the span subgroups as it proceeds to the end of the span group.Type: GrantFiled: May 24, 1999Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Charles Ray Johns, John Samuel Liberty, Brad William Michael, John Fred Spannaus