Patents by Inventor Brad Zwernemann

Brad Zwernemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250056156
    Abstract: A computer having a system for mitigating mechanical rattle arising due to a mechanical coupling of an audio output transducer to a part of the computer device, the system comprising: a processing subsystem configured to receive an input audio signal and to output a drive signal for driving the audio output transducer to produce a transducer output, wherein the processing subsystem is configured to selectively apply an attenuation function to the input audio signal to attenuate a signal component of the input audio signal at a frequency that causes mechanical rattle in the computer; and an analyser subsystem configured to receive the input audio signal and to output a control signal to the processing subsystem to control application of the attenuation function to the input audio signal by the processing subsystem based on a spectral content of the received input audio signal; wherein the attenuation function is based on characteristic acoustic behaviour of the computer.
    Type: Application
    Filed: August 6, 2024
    Publication date: February 13, 2025
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Peter FOSKEY, Kurt EFAW, Brad ZWERNEMANN, Enrique PEREZ BENAVIDES, Andrew RUMELT, Christopher JACKSON, Marco A. JANKO, William E. SHERWOOD, James E. BARKULOO
  • Patent number: 12149899
    Abstract: Circuitry for acoustic crosstalk cancellation between first and second acoustic signals, the circuitry comprising: crosstalk cancellation circuitry configured to: receive a first audio signal and, based on the received first audio signal, generate a first crosstalk cancellation signal; receive a second audio signal and, based on the received second audio signal, generate a second crosstalk cancellation signal; combine the first crosstalk cancellation signal with a signal indicative of the second audio signal to generate a first crosstalk cancellation circuitry output signal; and combine the second crosstalk cancellation signal with a signal indicative of the first audio signal to generate a second crosstalk cancellation circuitry output signal; and output stage circuitry configured to: receive the first crosstalk cancellation circuitry output signal and, based on the received first crosstalk cancellation circuitry, generate a first drive signal for driving a first speaker to generate the first acoustic signal
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: November 19, 2024
    Assignee: Cirrus Logic Inc.
    Inventors: Dayong Zhou, Brad Zwernemann, Kaichow Lau, Dana J. Taipale, John L. Melanson
  • Publication number: 20230421951
    Abstract: Circuitry for acoustic crosstalk cancellation between first and second acoustic signals, the circuitry comprising: crosstalk cancellation circuitry configured to: receive a first audio signal and, based on the received first audio signal, generate a first crosstalk cancellation signal; receive a second audio signal and, based on the received second audio signal, generate a second crosstalk cancellation signal; combine the first crosstalk cancellation signal with a signal indicative of the second audio signal to generate a first crosstalk cancellation circuitry output signal; and combine the second crosstalk cancellation signal with a signal indicative of the first audio signal to generate a second crosstalk cancellation circuitry output signal; and output stage circuitry configured to: receive the first crosstalk cancellation circuitry output signal and, based on the received first crosstalk cancellation circuitry, generate a first drive signal for driving a first speaker to generate the first acoustic signal
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dayong ZHOU, Brad ZWERNEMANN, Kaichow LAU, Dana J. TAIPALE, John L. MELANSON
  • Patent number: 11477569
    Abstract: A method of obtaining a directional microphone signal, the method comprising: receiving first and second microphone signals from first and second microphones separated by a distance; obtaining a combined microphone signal based on one or more of the first and second microphone signals; obtaining a difference microphone signal by subtracting the second microphone signal from the first microphone signal; obtaining a transformed combined microphone signal by applying a Hilbert transform to the combined microphone signal; combining the transformed combined microphone signal with the difference microphone signal to obtain the directional microphone signal.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: October 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Dayong Zhou, Brad Zwernemann
  • Publication number: 20220303673
    Abstract: A method of obtaining a directional microphone signal, the method comprising: receiving first and second microphone signals from first and second microphones separated by a distance; obtaining a combined microphone signal based on one or more of the first and second microphone signals; obtaining a difference microphone signal by subtracting the second microphone signal from the first microphone signal; obtaining a transformed combined microphone signal by applying a Hilbert transform to the combined microphone signal; combining the transformed combined microphone signal with the difference microphone signal to obtain the directional microphone signal.
    Type: Application
    Filed: March 18, 2021
    Publication date: September 22, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Dayong ZHOU, Brad ZWERNEMANN
  • Publication number: 20070211743
    Abstract: Methods and corresponding systems for allocating processing resources for a number of instances (N) of a software component include determining an average processing cost (?) and a variance (?2) for the software component. Then a processing cost for the software component is estimated as a function of N, the average processing cost (?), and the variance (?2), and processing resources are allocated in response to the estimated processing cost. The software component can be partitioned into a number of blocks (L), wherein the L blocks include a required block and one or more optional blocks. In some embodiments in response to a total estimated processing cost exceeding an available processing value, selected optional blocks can be disabled to reduce the total estimated processing cost to a value equal to or less than the available processing value. The optional blocks can be prioritized and disabled in order of priority.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 13, 2007
    Inventors: Brad Zwernemann, Roman Dyba, Perry He, Lucio Pessoa