Abstract: An XOR unit is provided in a hard disk controller for calculating an XOR of two operands stored in a buffer memory. The XOR unit includes an XOR calculator for calculating the XOR of the operands and a CRC of the XOR resulting from the calculation. An XOR buffer is also included in the XOR unit for storing the XOR result and the CRC of the XOR result, and a CRC calculator for calculating a CRC of the XOR result stored in the XOR buffer. The CRC calculated by the CRC calculator is compared with the CRC of the XOR result stored in the CRC buffer to determine whether the XOR result has been corrupted in the XOR buffer. The XOR result stored in the XOR buffer is determined to be corrupted if the CRC calculated by the CRC calculator and the CRC stored in the XOR buffer do not match.

Abstract: An XOR unit is provided in a hard disk controller for calculating an XOR of two operands stored in a buffer memory. The XOR unit includes an XOR calculator for calculating the XOR of the operands and a CRC of the XOR resulting from the calculation. An XOR buffer is also included in the XOR unit for storing the XOR result and the CRC of the XOR result, and a CRC calculator for calculating a CRC of the XOR result stored in the XOR buffer. The CRC calculated by the CRC calculator is compared with the CRC of the XOR result stored in the CRC buffer to determine whether the XOR result has been corrupted in the XOR buffer. The XOR result stored in the XOR buffer is determined to be corrupted if the CRC calculated by the CRC calculator and the CRC stored in the XOR buffer do not match.

Abstract: Apparatus for controlling input clock signals to a microprocessor includes a clock generator for generating the input clock signals to the microprocessor, and a clock controller for producing a control signal for disabling the clock generator from outputting the input clock signals to the microprocessor for a predetermined time. The clock generator resumes outputting the input clock signals to the microprocessor after the predetermined time.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: Data (e.g. legacy LAN traffic) segmented into packets provide a header and a cell payload for each cell in each packet. The cell payloads are transferred to a region address in a host memory in accordance with determinations by a control memory. When the cell payload is to be transmitted from the host memory, the cell payload for a particular region address is combined with the header stored in the control memory for such address. Streaming data (e.g. voice or video) occurs at a regular rate and is not necessarily broken into packets. The streaming data is segmented to provide cell headers and cell payloads. The cell payloads are then transferred to a host receive FIFO in accordance with a determination by the control memory and are stored in a data sink. Cell payloads from a data source are transferred into a host transmit FIFO at a particular rate and are transferred from the host transmit FIFO preferably at a substantially constant rate higher than the particular rate.

Abstract: An ATM system transmits different types of cells (data, forward resource management (RM) and backward RM) from station A through switch(es) to station B. Different fields in an Available Bit Rate (ABR) table provide controls over the rate of such cell transmissions. First particular field values in such table control the selection of successive ones of cell decision blocks which determine the type of cell to be transmitted. Second particular field values in such table control the selection of one of a plurality of entries in an exponent table which also provides other parameter values controlling the generation of an explicit rate. Third particular field values in the ABR table control the selection of an individual one of a plurality of rate decision blocks each indicating an individual rate of cell transmission from the station A to the station B.

Abstract: A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements.

Abstract: A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell payloads to a first line interfacing the SAR, the host writes the SAR that it has such cell payloads. The host writes the host buffer descriptors into the control queue to obtain the transfer of the buffer payload to the first line. The SAR writes the status queue when the transfer has been completed. To transfer cell payloads to the host memory, the host writes into the control queue the address of the buffers to receive the payload from the SAR. The SAR then writes the buffer descriptors to the status queue to obtain the transfer of the cell payloads to the buffers. Each of the control and status queues may be respectively considered to constitute two (2) control queues and two (2) status queues.

Abstract: An asynchronous transfer mode scheduler schedules connection utilizing available bit rate (ABR) modes of traffic, unspecified bit rate (UBR) modes of traffic, variable bit rate (VBR) modes of traffic, and constant bit rate (CBR) modes of traffic. The scheduler communicates with a dynamic schedule table which includes a programmable number of slots. Each slot includes a CBR entry, a tunnel entry, and a number of VBR entries. The VBR entries store a slot tail pointer which indicates the end of a linked list. The scheduler utilizes the single bucket algorithm or dual bucket algorithm to dynamically schedule connections on future slots. The scheduler places connections using the VBR mode of traffic in a priority queue and takes the highest priority connection in the priority queue for transmission on the network.

Abstract: An ATM system transmits different types of cells (data, forward resource management (RM) and backward RM) from station A through switch(es) to station B. Different fields in an Available Bit Rate (ABR) table provide controls over the rate of such cell transmissions. First particular field values in such table control the selection of successive ones of cell decision blocks which determine the type of cell to be transmitted. Second particular field values in such table control the selection of one of a plurality of entries in an exponent table which also provides other parameter values controlling the generation of an explicit rate. Third particular field values in the ABR table control the selection of an individual one of a plurality of rate decision blocks each indicating an individual rate of cell transmission from the station A to the station B.

Abstract: A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions.

Abstract: An asynchronous transfer mode scheduler schedules connection utilizing available bit rate (ABR) modes of traffic, unspecified bit rate (UBR) modes of traffic, variable bit rate (VBR) modes of traffic, and constant bit rate (CBR) modes of traffic. The scheduler communicates with a dynamic schedule table which includes a programmable number of slots. Each slot includes a CBR entry, a tunnel entry, and a number of VBR entries. The VBR entries store a slot tail pointer which indicates the end of a linked list. The scheduler utilizes the single bucket algorithm or dual bucket algorithm to dynamically schedule connections on future slots. The scheduler places connections using the VBR mode of traffic in a priority queue and takes the highest priority connection in the priority queue for transmission on the network.

Abstract: A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and the region length. The payload is recorded in such region. The control memory also provides a second host-memory region address, and length, when the payload length exceeds the payload length in the first address region. For transfer from the host memory to the cell interface, the control memory provides a host memory region address and the header combines the header and the payload and passes the combination to the cell interface. Cells from different sources (i.e. terminals) are scheduled at table positions dependent upon their individual transfer rates. The cells at the scheduled positions are normally transferred in time slots corresponding to such positions.