Abstract: A method for interconnecting nodes in each of a number of nets. This invention involves generating initial zones for all nets and determining cumulative demand for path spaces needed by these initial zones. The demand is then compared with the supply, and scores are determined for the paths of the initial zones. Redundant paths with the worst scores are then gradually deleted until there are no redundant paths. If however, demand for path spaces still exceeds supply, expanded zones are generated in areas where demand exceeds supply and redundant paths are gradually deleted until there are no redundant paths. The paths remaining after deletion from the expanded zones are then used to interconnect the nodes of the nets. The nodes are then interconnected using the remaining paths.

Abstract: A VLSI chip has multiple annular rings of circuit cells, interspersed with annular wiring channels for interconnecting the cells. Another wiring layer runs perpendicular to the rings. A central chip area contains all the I/O connections for the chip.

Abstract: Concentric patterns of cells or macros (1) and conductive lines 13 conserve space on a substrate having two conductive levels. Macros (1) occupy only the first metal level and lines 13 are on the second metal level. The second metal level may also contain concentric patterns of power buses 20 and ground buses 20.